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参数资料
| 型号： | NC7SZ175P6X_F40 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC FLIP FLOP SGL UHS D SC70-6 |
| 标准包装： | 3,000 |
| 系列： | 7SZ |
| 功能： | 复位 |
| 类型： | D 型 |
| 输出类型： | 非反相 |
| 元件数： | 1 |
| 每个元件的位元数： | 1 |
| 频率 - 时钟： | 100MHz |
| 延迟时间 - 传输： | 9.8ns |
| 触发器类型： | 正边沿 |
| 输出电流高，低： | 32mA，32mA |
| 电源电压： | 1.65 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 包装： | 带卷 (TR) |
www.fairchildsemi.com
4
NC7SZ175
AC Electrical Characteristics
Capacitance (Note 3)
Note 3: TA = +25C, f = 1MHz.
Note 4: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2)
CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN) + (ICCstatic).
Symbol
Parameter
VCC
TA = +25°CTA = 40°C to +85°C
Units
Conditions
Figure
(V)
Min
Typ
Max
Min
Max
Number
fMAX
Maximum Clock
1.65
100
MHz
Figures
1, 4
Frequency
1.8
100
2.5
± 0.2
125
CL = 50 pF
3.3
± 0.3
150
RL = 500
5.0
± 0.5
175
tPLH
Propagation Delay
1.65
2.5
9.8
15.0
2.5
16.5
ns
Figures
1, 3
tPHL
CP to Q
1.8
2.5
6.5
10.0
2.5
11.0
2.5
± 0.2
2.0
3.8
6.5
2.0
7.0
CL = 15 pF
3.3
± 0.3
1.5
2.8
4.5
1.4
5.0
RL = 1 M
5.0
± 0.5
1.0
2.2
3.5
1.0
3.8
3.3
± 0.3
2.0
3.4
5.5
1.6
6.2
CL = 50 pF
Figures
1, 3
5.0
± 0.5
1.5
2.6
4.0
1.4
4.7
RL = 500
tPHL
Propagation Delay
1.65
2.5
9.8
13.5
2.5
15.0
ns
Figures
1, 3
C to Q
1.8
2.5
6.5
9.0
2.5
10.0
2.5
± 0.2
2.0
3.8
6.0
2.0
6.4
CL = 15 pF
3.3
± 0.3
1.5
2.8
4.3
1.2
4.6
RL = 1 M
5.0
± 0.5
1.5
2.2
3.2
1.0
3.5
3.3
± 0.3
1.5
3.4
5.3
1.5
5.8
CL = 50 pF
Figures
1, 3
5.0
± 0.5
1.0
2.7
4.0
1.2
4.5
RL = 500
tS
Setup Time
2.5
± 0.2
2.5
ns
CL = 50 pF
Figures
1, 4
CP to D
3.3
± 0.3
2.0
RL = 500
5.0
± 0.5
1.5
tH
Hold Time,
2.5
± 0.2
1.5
ns
CL = 50 pF
Figures
1, 4
CP to D
3.3
± 0.3
1.5
RL = 500
5.0
± 0.5
1.5
tW
Pulse Width, CP
2.5
± 0.2
3.0
CL = 50 pF
Figures
1, 4
3.3
± 0.3
2.8
ns
RL = 500
5.0
± 0.5
2.5
Pulse Width, C
2.5
± 0.2
3.0
Clock HIGH or LOW
Figures
1, 4
3.3
± 0.3
2.8
ns
CL = 50 pF
5.0
± 0.5
2.5
RL = 500
trec
Recovery Time,
2.5
± 0.2
1.0
CL = 50 pF
Figures
1, 4
C to CP
3.3
± 0.3
1.0
ns
RL = 500
5.0
± 0.5
1.0
Symbol
Parameter
Typ
Max
Units
Conditions
CIN
Input Capacitance
3
pF
VCC = Open, VIN = 0V or VCC
COUT
Output Capacitance
4
pF
VCC = 3.3V, VIN = 0V or VCC
CPD
Power Dissipation Capacitance
10
pF
VCC = 3.3V
(Note 4)
12
VCC = 5.0V
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