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参数资料
| 型号： | NCL30051LEDGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NCL30051 LED DRIVER |
| 设计资源： | NCL30051LEDGEVB Schematic NCL30051LEDGEVB Test Procedure NCL30051LEDGEVB Gerber Zip NCL30051LEDGEVB Bill of Materials |
| 标准包装： | 1 |
| 电流 - 输出 / 通道： | 1A |
| 输出及类型： | 1，隔离 |
| 输出电压： | 35 ~ 50 V |
| 特点： | 可调光 |
| 输入电压： | 90 ~ 265VAC |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCL30051 |
| 其它名称： | NCL30051LEDGEVB-ND NCL30051LEDGEVBOS |
NCL30051
PFC Regulator
The PFC inductor current, I L(t) , reaches zero at the end
of the switch cycle as shown in Figure 4 and the average
input current, I in(t) , is in phase with the ac line voltage,
V in(t) .
V in (t)
I L (t)
PZCD
PControl
V D D
10V > 5.65 V
Clamp
< 2.25 V
Clamp
PFC
Error
Amplifier
+
ZCD
Comparator
V ZCD
S Q
Dominant
Reset
Latch
R Q
PFB
I PFB
+
I in (t)
V D D
?
V PREF
t
PCT
I PCT(C)
Level
Shifter
On time
Comparator
PFC OVP
Comparator
V CC Good
V PUVP
PFC MOSFET
Drive Signal
t
Figure 4. Inductor Current in CrM
High power factor is achieved in CrM by maintaining a
constant on time (t on ) for a given RMS input voltage
(V ac(RMS) ) and load conditions. Equation 2 shows the
relationship between on time and system operating
PCS
LEB
+
PFC UVP V POVP
Comparator ?
+
?
PCS
Comparator
PFCoff
2 @ P out @ L
h @ V ac(RMS) 2
V PCS(ILIM)
conditions.
t on + (eq. 2)
where, P out is the output power, L is the PFC inductor
inductance and h is the system efficiency.
On Time Control
The NCL30051 controls the on time by charging an
external timing capacitor on the PCT pin, C T , with a
constant current source, I PCT(C) . The C T ramp is then
compared to the control voltage, V PControl . The control
voltage is constant for a given RMS line voltage and output
load, satisfying Equation 2. The block diagram of the
constant on time section is shown in Figure 5.
+
?
Figure 5. Constant On Time Control Block Diagram
The PControl voltage is internally clamped between
2.25 V and 5.65 V. A voltage offset, V PCT(offset) , is added
to the C T ramp to account for the control voltage range.
This allows the PFC stage to stop the drive pulses (0% duty
ratio) and regulate at light loads. The delta between the
PControl voltage needed to generate a PDRV pulse and the
minimum PControl Clamp voltage is V PCT(offset) .
The timing capacitor is discharged and held low once the
C T ramp voltage plus offset reaches V PControl . The PFC
drive pulse terminates once the C T voltage reaches its peak
voltage threshold, V PCT(peak) . A new cycle starts once the
inductor current reaches zero detected by a transition on the
ZCD pin or the maximum off time has been reached.
The timing capacitor is sized such that the C T ramp peak
voltage is reached at low line and full load. In this operating
mode V PControl is at its maximum. Equation 3 is used to
calculate the on time for a given C T .
t on(MAX) +
C T @ V PCT(peak)
I PCT(C)
(eq. 3)
Substituting t on in Equation 2 with Equation 3 and
rearranging Equation 4 provides a maximum value for C T .
C T w
2 @ P out @ L @ I PCT(C)
h @ V ac(RMS) 2 @ V PCT(peak)
(eq. 4)
where, V PCT(peak) , is the maximum PCT voltage, typically
3.0 V.
http://onsemi.com
12
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