参数资料
| 型号： | NCN2500MNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 1CHAN USB 16-QFN |
| 产品变化通告： | Discontinuation 30/Jun/2006 |
| 标准包装： | 3,000 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | USB 2.0 |
| 电源电压： | 1.5 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 带卷 (TR) |
NCN2500
http://onsemi.com
3
PIN FUNCTION DESCRIPTION
Pin
Symbol
Function
Description
1
DSPD
INPUT
The DSPD logic level (Data Speed) activates the Low or the High speed
operation on the USB port.
DSPD = Low
Low Speed, RPU1 and RPU2 connected to D
DSPD = High
Full Speed, RPU1 and RPU2 connected to D+
2
RCV
OUTPUT
This pin interfaces the USB signals with the microcontroller digital line. The data
present on the D+/D pins are translated onto this signal.
3
Vp
I/O
This pin, associated with Vm, is an I/O system interface signal depending upon
the OE logic state:
OE = Low
Vp is a Plus driver Input (from
mC to USB bus)
OE = High
Vp is a Plus receiver Output (from USB bus to
mC)
4
Vm
I/O
This pin, associated with Vp, is an I/O system interface signal depending upon the
OE logic state:
OE = Low
Vm is a Minus driver Input (from
mC to USB bus)
OE = High
Vm is a Minus receiver Output (from USB bus to
mC)
5
EN_VObus
INPUT
Digital input to control the VObus voltage.
EN_VObus = Low
VObus connected to Vreg
EN_VObus = High
VObus disconnected from Vreg (Hi Z)
6
GND
PWR
This pin carries the digital and USB ground level. High Quality PCB design shall
be observed to avoid uncontrolled voltage spikes.
7
SPND
INPUT
The SPND digital signal (SUSPEND) selects the operation mode to reduce the
power supply current.
SPND = Low
Normal operation
SPND = High
Suspend mode, no activity takes place
8
NC
No Connection, shall be neither grounded, nor connected to Vcc or Vbus.
9
OE
INPUT
This pin activates the operating mode of the D/D+ signals.
OE = Low logic level
Data are transmitted onto the USB bus
OE = High logic level
Data are received from the USB bus
10
D
I/O
This pin is connected to the USB Minus Data line I/O. The data direction depends
upon the OE logic state.
11
D+
I/O
This pin is connected to the USB Plus Data line I/O The data direction depends
upon the OE logic state.
12
Vreg
PWR
This pin provides a 3.3 V regulated voltage to supply the internal USB blocks and
the external termination bias resistor. An external circuit can be connected to this
LDO, assuming the current does not extend the maximum rating (50 mA).
13
VObus
OUTPUT, PWR
This pin connects the Vreg voltage to the 1.5 k external pullup resistor. The
VObus voltage is controlled by the logic states present Pin 5. The RDSon of the
internal PMOS device (reference S5 in the Block Diagram) is 10
W typical.
14
Vusb
PWR
This pin is connected to the USB port +Vcc supply voltage.
15
Vcc
PWR
This pin provides the interface power supply. The power source can be an
external supply or can be derived from the USB + Vusb voltage.
16
EN_RPU
INPUT
This pin activates or deactivate the internal RPU1 and RPU2 pullup resistors:
EN_RPU = H
RPU1 and RPU2 activated
EN_RPU = L
RPU1 and RPU2 deactivated
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