参数资料
| 型号： | NCN4557MTG |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | IC SMART CARD/SIM DUAL 16-QFN |
| 产品变化通告： | Product Discontinuation 30/Sept/2011 |
| 标准包装： | 123 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
NCN4557
http://onsemi.com
10
18 k
CRD_I/O
14 k
I/O
VDD
LOGIC
IO/CONTROL
GND
200 ns
Q1
Q2
Q3
CRD_VCC
Figure 10. Basic I/O line Interface
The typical waveform provided in Figure 11 shows how
the accelerator operates. During the first 200 ns (typical),
the slope of the rise time is solely a function of the pullup
resistor associated with the stray capacitance. During this
period, the PMOS devices are not activated since the input
voltage is below their Vgs threshold. When the input slope
crosses the Vgsth, the opposite one shot is activated,
providing a low impedance to charge the capacitance, thus
increasing the rise time as depicted in Figure 11. The same
mechanism applies for the opposite side of the line to make
sure the system is optimum.
Figure 11. CRD_IO Typical Rise and Fall Times
with Stray Capacitance > 30 pF
(33 pF capacitor connected on the board)
Powerup Sequence
The powerup sequence makes sure all the cardrelated
signals are LOW during the CRD_VCC positive going
slope. The Powerup sequence is activated by setting the
ENABLE Boolean signal HIGH. CRD_RST, CRD_CLK
and CRD_I/O are maintained LOW during the activation
stage until CRD_VCC reaches its nominal value (1.8 V or
3.0 V). Figure 7 shows the typical NCN4557 activation
sequence.
About 800
ms after CRD_VCC has reached its nominal
voltage value, CRD_IO and CRD_RST are released.
CRD_CLK is enabled during the rising slope of the
second clock cycle after CRD_IO and CRD_RST are
enabled.
Figure 12. NCN4557 PowerUp
CRD_RSTA/B
CRD_IOA/B
CRD_CLKA/B
CRD_VCCA/B
ENABLE
TON ~ 0.9 ms
2nd Rise Edge After
CRD_IOA/B Rising
In all cases the application software is responsible for the
smart card signal sequence (contact activation sequence,
cold reset and warm reset sequences).
Powerdown Sequence
The NCN4557 provides a powerdown sequence which is
activated by setting the ENABLE Boolean signal LOW.
The communication I/O session is terminated immediately
according to the ISO7816 and EMV specifications as
ISO7816 Sequence:
CRD_RST is forced to LOW
CRD_CLK is forced to LOW 2 clock cycles after
ENABLE is set LOW unless CRD_CLK is already in
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