参数资料
| 型号： | NCN5192MNRG |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/13页 |
| 文件大小： | 0K |
| 描述： | IC HART MODEM CMOS SGL 32QFN |
| 标准包装： | 1 |
| 系列： | * |
NCN5192
http://onsemi.com
9
Receive Filter and Comparator
The received FSK signal first is filtered using a band-pass
filter build around the low noise receiver operational
amplifier “Rx HP filter”. This filter blocks interferences
outside the HART signal band.
Rx Comp
Rx HP Filter
RxAF
RxA
RxAFI
AREF
DEMODULATOR
HART IN
1.235 VDC
C1
C2
C3
R1
R2
R3
R4
R6
R5
C4
PC20101118 .2
15
M
W
Figure 8. Demodulator Receive Filter and Signal
Comparator
The filter output is fed into the Rx comparator. The
threshold value equals the analog ground making the
comparator to toggle on every zero crossing of the filtered
FSK signal. The maximum demodulator jitter is 12 % of one
bit given the input frequencies are within the HART
specifications, a clock frequency of 460.8 kHz (
±1.0 %) and
zero input (RxA) asymmetry.
Carrier Detect Circuitry
Low HART input signal levels increases the risk for the
generation of bit errors. Therefore the minimum signal
amplitude is set to 80120 mVpp. If the received signal is
below this level the demodulator is disabled.
This level detection is done in the Carrier Detector. The
output of the demodulator is qualified with the carrier detect
signal (CD), therefore, only RxA signals large enough to be
detected (100 mVp-p typically) by the carrier detect circuit
produce received serial data at RxD.
Figure 9. Demodulator Carrier and Signal
Comparator
RxD
CD
Demodulator
Logic
Rx Comp
Carrier Detect
Counter
Carrier Comp
DEMODULATOR
RxAFI
AREF
CDREF
15
M
W
FILTERED
HART IN
1.235 VDC
VAREF –80 mV
KVDE20110407.6
RxD_ENH
The carrier detect comparator shown in Figure 9 generates
logic low output if the RxAFI voltage is below CDREF. The
comparator output is fed into a carrier detect block. The
carrier detect block drives the carrier detect output pin CD
high if RTSB is high and four consecutive pulses out of the
comparator have arrived. CD stays high as long as RTSB is
high and the next comparator pulse is received in less than
2.5 ms. Once CD goes inactive, it takes four consecutive
pulses out of the comparator to assert CD again. Four
consecutive pulses amount to 3.33 ms when the received
signal is 1200 Hz and to 1.82 ms when the received signal
is 2200 HZ. The difference between RxD and RxD_ENH is
evident when CD is low: RxD is then also low, while
RxD_ENH is then high. When CD is high, RxD and
RxD_ENH have the same output.
Miscellaneous Analog Circuitry
Voltage References
The NCN5192 requires two voltage references, AREF
and CDREF. AREF sets the DC operating point of the
internal operational amplifiers and is the reference for the
Rx comparator. If NCN5192 operates at VDD = 3.3 V the ON
Semiconductor
LM285D
1.235
V
reference
is
recommended.
The level at which CD (Carrier Detect) becomes active is
determined by the DC voltage difference (CDREF - AREF).
Selecting a voltage difference of 80 mV will set the carrier
detect to a nominal 100 mVp-p.
Bias Current Resistor
The NCN5192 requires a bias current resistor RBIAS to be
connected between CBIAS and VSS. The bias current
controls the operating parameters of the internal operational
amplifiers and comparators and should be set to 2.5
mA.
BIAS
CBIAS
OPA
AREF
2.
5
m
A
RBIAS
PC20101118 .4
Figure 10. Bias Circuit
The value of the bias current resistor is determined by the
reference voltage AREF and the following formula:
RBIAS + AREF
2.5 mA
The recommended bias current resistor is 500 K
W when
AREF is equal to 1.235 V.
Oscillator
The clock signal used by NCN5192 can either be
460.8 kHz, 921.6 kHz or 1.8432 MHz. This can be provided
by an external clock or a resonator or crystal connected to the
internal oscillator.
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