参数资料
型号: NCN6004AFTBR2
厂商: ON Semiconductor
文件页数: 8/40页
文件大小: 0K
描述: IC INTERFACE SAM/SIM DUAL 48TQFP
标准包装: 1
应用: PC,PDA
接口: 微控制器
电源电压: 1.8 V ~ 5.5 V
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP(7x7)
包装: 剪切带 (CT)
安装类型: 表面贴装
其它名称: NCN6004AFTBR2OSCT
NCN6004A
http://onsemi.com
16
Table 3. Status Pins Data
STATE
(HEX)
PGM
A3
A2
A1
A0
CARD_SEL
STATUS #A
STATUS #B
00
1
X
0
X
Vcc_Vbat_OK Pass = Low
VCC_OK Fail = High
01
1
X
0
1
CRD_VCC_A In Range
Pass = High Fail =Low
02
1
X
1
0
1
CRD_VCCA Overloaded
Pass = High Fail = Low
03
1
X
1
CRD_DET_A
Card Present = High
00
1
X
0
X
VCC_OK Pass = Low
VCC_OK Fail = High
01
1
X
0
1
0
CRD_VCC_B In Range
Pass = High Fail =Low
02
1
X
1
0
CRD_VCC_B Overloaded
Pass = High Fail = Low
03
1
X
1
0
CRD_DET_A
Card Present = High
*The STATUS register is not affected when the NCN6004A operates in any of the programming mode.
Initialized conditions upon startup are depicted by bold characters in Table 2 and Table 4.
Vbat
2.10 V
2.00 V
2.70 V
3.30 V
Vbat_OK
Vbat STATUS
Max. ANLG_VCC Under Voltage
Min. ANLG_VCC Under Voltage
Typical ANLG_VCC Operating Voltage
The input power supply voltage monitoring applies to the card selected.
Figure 5. Reading ANLG_VCC Status (monitoring ANLG_VCC input voltage)
SYSTEM STATES UPON UPON STARTUP
Table 4. Operating Conditions Upon Startup
CRD_VCC_A
3.0 V
CRD_VCC_B
3.0 V
CRD_CLK_A
1/1 Ratio
CRD_CLK_B
1/1 Ratio
CRD_CLK_A
START (clock is valid)
CRD_CLK_B
START (clock is valid)
CRD_CLK_A
Low Speed Slope
CRD_CLK_B
Low Speed Slope
CLOCK Route
Direct (CLK_A
→ A, CLK_B → B)
Depending upon the logic state at turn on present on
pin 44, the system will run into a parallel mode
(MUX_MODE = L)
or
a
multiplexed
mode
(MUX_MODE = H). It is not possible to change the logic
state once the system is running.
Similarly, depending upon the logic state present pin 45,
the internal pull up resistors (I/O_A and I/O_B line) will be
either connected to ANLG_VCC voltage (EN_RPU = H) or
disconnected (EN_RPU = L). It is not possible to change this
operating condition once the system is running.
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