参数资料
型号: NCP1012APL065R2G
厂商: ON Semiconductor
文件页数: 16/24页
文件大小: 0K
描述: IC OFFLINE SW SMPS CM OVP 7DIPGW
标准包装: 1
输出隔离: 隔离
频率范围: 59kHz ~ 71kHz
输入电压: 8.5 V ~ 10 V
输出电压: 700V
功率(瓦特): 19W
工作温度: -40°C ~ 125°C
封装/外壳: 8-SMD(7 个接脚),鸥形翼
供应商设备封装: 7-PDIP,鸥翼型
包装: 剪切带 (CT)
其它名称: NCP1012APL065R2GOSCT
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
350
250
150
50.0
> 0 !!
--50.0
1.004M
1.011M
1.018M
1.025M
1.032M
Figure 26. The Drain--Source Wave Shall Always be Positive . . .
Lp · Ip
ton =
N · (Vout + Vf)
. toff, the OFF time is thus:
Lp · Ip
toff =
1. In any case, the lateral MOSFET body--diode shall
never be forward biased, either during startup
(because of a large leakage inductance) or in
normal operation as shown by Figure 26.
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N · (Vout + Vf) < Vin min (eq. 14) . For instance, if
operating from a 120 V DC rail, with a delivery of 12 V, we
can select a reflected voltage of 100 Vdc maximum:
120–100 > 0. Therefore, the turn ratio Np:Ns must be
smaller than 100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see
later on how it affects the calculation.
2. A current--mode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a duty--cycle greater
than 50%. As a result, we recommend to operate
the device in DCM only, whatever duty--cycle it
implies (max = 65%). However, CCM operation
with duty--cycles below 40% is possible.
3. Lateral MOSFETs have a poorly dopped
body--diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications,
a simple capacitor can also be used since
Lf
Vdrain max = Vin + N · (Vout + Vf) + Ip · ? Ctot
(eq. 15) , where Lf is the leakage inductance,
Ctot is the total capacitance at the drain node
(which is increased by the capacitor wired between
drain and source), N the Np:Ns turn ratio, Vout the
output voltage, Vf the secondary diode forward
drop and finally, Ip the maximum peak current.
Worse case occurs when the SMPS is very close to
regulation, e.g. the Vout target is almost reached
and Ip is still pushed to the maximum.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line.
When the switch closes, Vin is applied across the primary
inductance Lp until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
(eq. 16)
Vin
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across
Lp, resetting the transformer core with a slope of
Lp
(eq. 17)
N · (Vout + Vf)
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a dead--time after the
core is reset, but rather immediately restart. The switching
time can be expressed by:
1 1
Tsw = toff + ton = Lp · Ip · ? Vin + N · (Vout + Vf) ?
(eq. 18)
http://onsemi.com
16
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