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参数资料
| 型号： | NCP1014APL065R2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC OFFLINE SW SMPS CM OVP 7DIPGW |
| 标准包装： | 1 |
| 输出隔离： | 隔离 |
| 频率范围： | 59kHz ~ 71kHz |
| 输入电压： | 8.1 V ~ 10 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 19W |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SMD（7 个接脚），鸥形翼 |
| 供应商设备封装： | 7-PDIP，鸥翼型 |
| 包装： | 标准包装 |
| 其它名称： | NCP1014APL065R2GOSDKR |
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Tsw
1 V Ripple
Tstart
TLatch
Latch--off
Level
Figure 16. NCP101X Facing a Fault Condition (Vin = 150 Vdc)
The rising slope from the latch--off level up to 8.5 V
Vds(t)
is expressed by: Tstart =
. The time during which
.
the IC actually pulses is given by tsw =
Finally, the latch--off time can be derived
Δ V1 · C
IC1
Δ V2 · C
ICC1
Vin
Vr
toff
dt
.
using the same formula topology: TLatch =
Δ V3 · C
ICC2
From these three definitions, the burst duty--cycle
(eq. 2) .
can be computed: dc =
(eq. 3) .
Feeding
the
dc =
ICC1 · ? ICC1 + Δ IC1 + ICC2 ?
Tsw
Tstart + Tsw + TLatch
Δ V2
Δ V2 V1 Δ V3
equation with values extracted from the parameter section
gives a typical duty--cycle of 13%, precluding any lethal
ton
Tsw
Figure 17. A typical drain--ground waveshape
where leakage effects are not accounted for.
t
< Vds(t) >= Vin · (1 ? d) + Vr · toff (eq. 5)
< Vds(t) >= Vin ? Vin · ton + Vr · toff (eq. 6)
toff can be expressed by: toff = Ip ·
(eq. 7) where ton
(eq. 8) .
can be evaluated by: ton = Ip ·
thermal runaway while in a fault condition.
DSS Internal Dissipation
The Dynamic Self--Supplied pulls energy out from the
drain pin. In Flyback--based converters, this drain level can
easily go above 600 V peak and thus increase the stress on the
DSS startup source. However, the drain voltage evolves with
time and its period is small compared to that of the DSS. As
a result, the averaged dissipation, excluding capacitive losses,
can be derived by: PDSS = ICC1 · < Vds(t) > . (eq. 4) .
Figure 17 portrays a typical drain--ground waveshape where
leakage effects have been removed.
By looking at Figure 17, the average result can easily be
derived by additive square area calculation:
Tsw
By developing Equation 5, we obtain:
Tsw Tsw
Lp
Vr
Lp
Vin
http://onsemi.com
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