参数资料
型号: NCP1080DEG
厂商: ON Semiconductor
文件页数: 8/15页
文件大小: 221K
描述: IC CONV CTLR POE-PD 13W 20-TSSOP
标准包装: 74
类型: 以太网供电开关(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
电流限制: 500mA
电源电压: 0 V ~ 57 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 20-TSSOP-EP
包装: 管件
NCP1080
http://onsemi.com
8
Table 3. OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
PASSSWITCH AND CURRENT LIMITS
Ron
Passswitch Rdson

0.6
1.2
W
Max Ron specified at
Tj = 130癈
I_Rinrush1
Rinrush = 150 kW (Note 7)
95
125
155
mA
Measured at RTN
VPORTN
1,2
 = 3 V
I_Rinrush2
Rinrush = 57.6 kW (Note 7)
260
310
360
mA
Measured at RTN
VPORTN
1,2
 = 3 V
I_Rilim1
Rilim1 = 84.5 kW (Note 7)
450
510
570
mA
Current limit threshold
INRUSH AND ILIM1 CURRENT LIMIT TRANSITION
Vds_pgood
VDS required for power good status
0.8
1
1.2
V
RTNVPORTN
1,2
falling; voltage with re-
spect to VPORTN
1,2
Vds_pgood_hyst
VDS hysteresis required for power good
status

8.2

V
Voltage with respect to
VPORTN
1,2
VDDH REGULATOR
VDDH_reg
Regulator output voltage (Notes 8 and 9)
Ivddh_load + Ivddl_load < 10 mA
with
0 < Ivddl_load < 2.25 mA
8.4
9
9.6
V
VDDH_Off
Regulator turnoff voltage

VDDH_reg
+ 0.5 V

V
For information only
VDDH_lim
VDDH regulator current limit
(Notes 8 and 9)
13

26
mA
VDDH_Por_R
VDDH POR level (rising)
7.3

8.3
V
VDDH_Por_F
VDDH POR level (falling)
6

7
V
VDDH_ovlo
VDDH overvoltage level (rising)
16

18.5
V
VDDL REGULATOR
VDDL_reg
Regulator output voltage (Notes 8 and 9)
0 < Ivddl_load < 2.25 mA
with
Ivddh_load + Ivddl_load < 10 mA
3.05
3.3
3.55
V
VDDL_Por_R
VDDL POR level (rising)
VDDL
 0.2

VDDL
 0.02
V
VDDL_Por_F
VDDL POR level (falling)
2.5

2.9
V
GATE DRIVER
Gate_Tr
GATE rise time (1090%)


50
ns
Cload = 2 nF,
VDDHreg = 9 V
Gate_Tf
GATE fall time (9010%)


50
ns
Cload = 2 nF,
VDDHreg = 9 V
PWM COMPARATOR
VCOMP
COMP control voltage range
1.3

3
V
For information only
7.  The current value corresponds to the PoEPD input current (the current flowing in the external Rdet and the quiescent current of the device
are included). Resistors are assumed to have 1% accuracy.
8.  Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.
9.  Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
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