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参数资料
| 型号： | NCP1082DEG |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/17页 |
| 文件大小： | 214K |
| 描述： | IC CONV CTLR POE-PD 13W 20-TSSOP |
| 标准包装： | 74 |
| 类型： | 以太网供电开关（PoE） |
| 应用： | 远程外设（工业控制，相机，数据访问） |
| 内部开关： | 是 |
| 电流限制： | 500mA |
| 电源电压： | 0 V ~ 57 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 20-TSSOP-EP |
| 包装： | 管件 |
NCP1082
http://onsemi.com
9
Table 3. OPERATING CONDITIONS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDH REGULATOR
VDDH_reg
Regulator output voltage
(Notes 10 and 11)
Ivddh_load + Ivddl_load < 10 mA
with Ivddl_load < 2.25 mA and
12.5 V < VPORTP ARTN < 57 V
8.4
9
9.6
V
VDDH_Off
Regulator turnoff voltage
For information only
VDDH_reg
+ 0.5 V
V
VDDH_lim
VDDH regulator current limit
(Notes 10 and 11)
13
26
mA
VDDH_Por_R
VDDH POR level (rising)
7.3
8.3
V
VDDH_Por_F
VDDH POR level (falling)
6
7
V
VDDH_ovlo
VDDH overvoltage level (rising)
16
18.5
V
VDDL REGULATOR
VDDL_reg
Regulator output voltage
(Notes 10 and 11)
Ivddl_load < 2.25 mA with
Ivddh_load + Ivddl_load < 10 mA
and 12.5 V < VPORTP
ARTN < 57 V
3.05
3.3
3.55
V
VDDL_Por_R
VDDL POR level (rising)
VDDL
0.2
VDDL
0.02
V
VDDL_Por_F
VDDL POR level (falling)
2.5
2.9
V
GATE DRIVER
Gate_Tr
GATE rise time (1090%)
Cload = 2 nF, VDDHreg = 9 V
50
ns
Gate_Tf
GATE fall time (9010%)
Cload = 2 nF, VDDHreg = 9 V
50
ns
PWM COMPARATOR
VCOMP
COMP control voltage range
For information only
1.3
3
V
ERROR AMPLIFIER
Vbg_fb
Reference voltage
Voltage with respect to ARTN
1.15
1.2
1.25
V
Av_ol
DC open loop gain
For information only
80
dB
GBW
Error amplifier GBW
For information only
1
MHz
SOFTSTART
Vss
Softstart voltage range
1.15
V
Vss_r
Softstart low threshold
(rising edge)
0.35
0.45
0.55
V
Iss
Softstart source current
3
5
7
mA
CURRENT LIMIT COMPARATOR
CSth
CS threshold voltage
324
360
396
mV
Tblank
Blanking time
For information only
100
ns
10.Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.
11.Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
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