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参数资料
| 型号： | NCP1083DER2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/18页 |
| 文件大小： | 257K |
| 描述： | IC CONV CTLR POE-PD 40W 20-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 以太网供电开关（PoE） |
| 应用： | 远程外设（工业控制，相机，数据访问） |
| 内部开关： | 是 |
| 电流限制： | 1.1A |
| 电源电压： | 0 V ~ 57 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 20-TSSOP-EP |
| 包装： | 带卷 (TR) |
NCP1083
http://onsemi.com
16
Both VDDH and VDDL regulators turn on as soon as
VPORT reaches the Vuvlo_on threshold.
Error Amplifier
In nonisolated converter topologies, the high gain
internal error amplifier of the NCP1083 and the internal
1.2 V reference voltage regulate the DCDC output voltage.
In this configuration, the feedback loop compensation
network should be inserted between the FB and COMP pins
as shown in Figures 3, 4 and 5.
In isolated topologies the error amplifier is not used
because it is already implemented externally with the shunt
regulator on the secondary side of the DCDC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the optocoupler has to
be connected on the COMP pin where an internal 5 kW
pullup resistor is tied to the VDDL supply (see Figure 16).
SoftStart
The softstart function provided by the NCP1083 allows
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor C
SS
between the SS
and ARTN pins.
While the DCDC controller is in POR, the capacitor C
SS
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
C
SS
to initiate softstart. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DCDC operation starts with a duty cycle limit which
increases with the SS pin voltage. The softstart function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
Softstart can be programmed by using the following
equation:
t
SS
(ms) + 0.23 C
SS
(nF)
Current Limit Comparator
The NCP1083 current limit block behind the CS pin
senses the current flowing in the external MOSFET for
current mode control and cyclebycycle current limit. This
is performed by the current limit comparator which, on the
CS pin, senses the voltage across the external Rcs resistor
located between the source of the MOSFET and the ARTN
pin.
The NCP1083 also provides a blanking time function on
CS pin which ensures that the current limit and PWM
comparators are not prematurely trigged by the current spike
that occurs when the switching MOSFET turns on.
Slope Compensation Circuitry
To overcome subharmonic oscillations and instability
problems that exist with converters running in continuous
conduction mode (CCM) and when the duty cycle is close
or above 50 percent, the NCP1083 integrates a current slope
compensation circuit. The amplitude of the added slope
compensation is typically 110 mV over one cycle.
As an example, for an operating switching frequency of
250 kHz, the internal slope provided by the NCP1083 is
27.5 mV/ mA typically.
DCDC Controller Oscillator
The frequency is configured with the Rosc resistor
inserted between OSC and ARTN, and is defined by the
following equation:
R
OSC
(kW) +
38600
F
OSC
(kHz)
The duty cycle limit is fixed internally at 80 percent.
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