参数资料
型号: NCP1237AD65R2G
厂商: ON Semiconductor
文件页数: 5/41页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 7SOIC
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 70kHz
占空比: 85%
电源电压: 9.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)7 引线
包装: 标准包装
其它名称: NCP1237AD65R2GOSDKR
NCP1237
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to +125 ° C, V HV = 120 V,
V CC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source operation
V HV(min)
?
?
60
V
Current flowing out of V CC pin @ V HV = 60 V
Off ? state leakage current
V CC = 0 V
V CC = V CC(on) ? 0.5 V
V HV = 500 V
I start1
I start2
I start(off)
0.2
4
?
0.5
8
25
0.8
12
50
mA
m A
SUPPLY
Turn ? on threshold level, V CC going up
HV current source stop threshold
HV current source restart threshold
Turn ? off threshold level
V CC(on)
V CC(min)
V CC(off)
11.0
9.5
8.5
12.0
10.5
9.5
13.0
11.5
10.5
V
V
V
Blanking duration on V CC(min) and V CC(off) detection
V CC decreasing level at which the internal logic resets
V CC level for I START1 to I START2 transition
Internal current consumption (Note 5)
Guaranteed by design
DRV open, V FB = 3 V
C drv = 1 nF, V FB = 3 V
Off mode (skip or before
startup)
Fault mode (fault or latch)
t UVLO(blank)
V CC(reset)
V CC(inhibit)
ICC1
ICC2
ICC3
ICC4
7
4.0
0.4
2.0
2.3
0.9
0.4
10
5.2
0.65
2.5
3.3
1.2
0.7
13
6.5
0.9
3.0
4.3
1.5
1.0
m s
V
V
mA
BROWN ? OUT AND LINE OVERVOLTAGE
Brown ? out threshold voltage
Timer duration for line cycle drop ? out
Overvoltage threshold
Blanking duration on line overvoltage detection
V HV going up
V HV going down
V HV going up
V HV going down
V HV(start)
V HV(stop)
t HV
V HV(OV1)
V HV(OV2)
t OV(blank)
104
97
43
400
395
?
112
105
61
430
425
250
120
113
79
460
455
?
V
ms
V
m s
OSCILLATOR
Oscillator frequency
Maximum duty ratio
f OSC
D MAX
60
75
65
80
70
85
kHz
%
Frequency jittering amplitude, in percentage of F OSC
Frequency jittering modulation frequency
Guaranteed by design
Guaranteed by design
A jitter
F jitter
$ 4
85
$ 6
125
$ 8
165
%
Hz
OUTPUT DRIVER
Rise time, 10% to 90% of V CC
Fall time, 90% to 10% of V CC
Current capability
Clamping voltage (maximum gate voltage)
High ? state voltage drop
V CC = V CC(min) + 0.2 V,
C DRV = 1 nF
V CC = V CC(min) + 0.2 V,
C DRV = 1 nF
V CC = V CC(min) + 0.2 V,
C DRV = 1 nF
DRV high, V DRV = 0 V
DRV low, V DRV = V CC
V CC = V CCmax – 0.2 V, DRV
high
V CC = V CC(min) + 0.2 V,
R DRV = 33 k W , DRV high
t rise
t fall
I DRV(source)
I DRV(sink)
V DRV(clamp)
V DRV(drop)
?
?
?
?
11
?
22
22
1000
1000
13.5
?
34
34
?
?
16
1
ns
ns
mA
V
V
5. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
http://onsemi.com
5
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