参数资料
型号: NCP1246AD065R2G
厂商: ON Semiconductor
文件页数: 6/39页
文件大小: 0K
描述: IC CTLR CURR MODE 65KHZ 8SOIC
标准包装: 2,500
系列: *
NCP1246
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to +125 ° C, V HV = 125 V,
V CC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Maximum duty cycle (corresponding to
maximum on time at maximum switching
frequency)
Frequency jittering amplitude, in percentage
of F OSC
Frequency jittering modulation frequency
f OSC = 65 kHz
f OSC = 100 kHz
D MAX
A jitter
F jitter
?
± 4
85
80
± 6
125
?
± 8
165
%
%
Hz
FREQUENCY FOLDBACK
Feedback voltage threshold below which
frequency foldback starts
Feedback voltage threshold below which
frequency foldback is complete
V FB(foldS)
V FB(foldE)
1.8
0.8
2.0
0.9
2.2
1.0
V
V
Minimum switching frequency
V FB = V skip(in) + 0.1
f OSC(min)
23
27
32
kHz
OUTPUT DRIVER
Rise time, 10 to 90% of V CC
Fall time, 90 to 10% of V CC
Current capability
Clamping voltage (maximum gate voltage)
High ? state voltage drop
V CC = V CC(min) + 0.2 V,
C DRV = 1 nF
V CC = V CC(min) + 0.2 V,
C DRV = 1 nF
V CC = V CC(min) + 0.2 V,
C DRV = 1 nF
DRV high, V DRV = 0 V
DRV low, V DRV = V CC
V CC = V CCmax – 0.2 V, DRV high,
R DRV = 33 k W , C load = 220 pF
V CC = V CC(min) + 0.2 V,
R DRV = 33 k W , DRV high
t rise
t fall
I DRV(source)
I DRV(sink)
V DRV(clamp)
V DRV(drop)
?
?
?
?
11
?
40
40
500
800
13.5
?
70
70
?
?
16
1
ns
ns
mA
V
V
CURRENT SENSE
Input Pull ? up Current
Maximum internal current setpoint
Propagation delay from V Ilimit detection to
DRV off
Leading Edge Blanking Duration for V ILIM
Threshold for immediate fault protection
activation
Leading Edge Blanking Duration for V CS(stop)
(Note 6)
Soft ? start duration
Frozen current setpoint
V CS = 0.7 V
V FB > 3.5 V
V CS = V ILIM
From 1 st pulse to V CS = V ILIM
I bias
V ILIM
t delay
t LEB
V CS(stop)
t BCS
t SSTART
V I(freeze)
?
0.66
?
200
0.95
90
8
275
1
0.70
80
250
1.05
120
11
300
?
0.74
110
320
1.15
150
14
325
m A
V
ns
ns
V
ns
ms
mV
INTERNAL SLOPE COMPENSATION
Slope of the compensation ramp
S comp(65kHz)
S comp(100kHz)
?
?
? 32.5
? 50
?
?
mV /
m s
FEEDBACK
Internal pull ? up resistor
V FB to internal current setpoint division ratio
T J = 25 ° C
R FB(up)
K FB
15
4.7
20
5
25
5.3
k W
?
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of I bias and I OPC , thus at V HV = 125 V is observed the I bias only, because I OPC is switched off.
http://onsemi.com
6
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