参数资料
| 型号： | NCP1271P65G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/21页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM CM OVP OTP HV 7DIP |
| 标准包装： | 1,000 |
| 系列： | Soft-Skip™ |
| 输出隔离： | 隔离 |
| 频率范围： | 55kHz ~ 69kHz |
| 输入电压： | 10 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm），7 引线 |
| 供应商设备封装： | 7-PDIP |
| 包装： | 管件 |
NCP1271
MAXIMUM RATINGS (Notes 1 and 2)
V CC Pin (Pin 6)
Maximum Voltage Range
Maximum Current
Rating
Symbol
V max
I max
Value
? 0.3 to +20
100
Unit
V
mA
Skip/Latch, FB, CS Pin (Pins 1 ? 3)
Maximum Voltage Range
Maximum Current
V max
I max
? 0.3 to +10
100
V
mA
Drv Pin (Pin 5)
Maximum Voltage Range
Maximum Current
V max
I max
? 0.3 to +20
? 800 to +500
V
mA
HV Pin (Pin 8)
Maximum Voltage Range
Maximum Current
V max
I max
? 0.3 to +500
100
V
mA
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction ? to ? Air, PDIP ? 7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction ? to ? Lead, PDIP ? 7, Low Conductivity PCB
Thermal Resistance, Junction ? to ? Air, PDIP ? 7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction ? to ? Lead, PDIP ? 7, High Conductivity PCB
Thermal Resistance, Junction ? to ? Air, SO ? 7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction ? to ? Lead, SO ? 7, Low Conductivity PCB
Thermal Resistance, Junction ? to ? Air, SO ? 7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction ? to ? Lead, SO ? 7, High Conductivity PCB
Operating Junction Temperature Range
Maximum Storage Temperature Range
R q JA
R q JL
R q JA
R q JL
R q JA
R q JL
R q JA
R q JL
T J
T stg
142
57
120
56
177
75
136
69
? 40 to +150
? 60 to +150
° C/W
° C/W
° C/W
° C/W
° C/W
° C/W
° C/W
° C/W
° C
° C
ESD Protection
Human Body Model ESD Pins 1 ? 6
Human Body Model ESD Pin 8
Machine Model ESD Pins 1 ? 4, 8
Machine Model ESD Pins 5, 6
Charged Device Model ESD
HBM
HBM
MM
MM
CDM
2000
700
200
150
1000
V
V
V
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. ESD protection per JEDEC JESD22 ? A114 ? F for HBM, per JEDEC JESD22 ? A115 ? A for MM, and per JEDEC JESD22 ? C101D for CDM.
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
2. Guaranteed by design, not tested.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm 2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
http://onsemi.com
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