参数资料
型号: NCP1337ADAPGEVB
厂商: ON Semiconductor
文件页数: 11/15页
文件大小: 0K
描述: EVAL BOARD FOR NCP1337ADAPG
设计资源: NCP1337 Adapter EVB BOM
NCP1337ADAPGEVB Gerber Files
NCP1337 Adapter EVB Schematic
标准包装: 1
系列: Greenpoint™
主要目的: AC/DC,主面
输出及类型: 1,隔离
功率 - 输出: 60W
输出电压: 12V
电流 - 输出: 5A
输入电压: 90 ~ 265VAC
稳压器拓扑结构: 回扫
频率 - 开关: 130kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP1337
其它名称: NCP1337ADAPGEVBOS
NCP1337
Soxyless
The “Valley point detection” is based on the observation
of the Power MOSFET Drain voltage variations. When the
transformer is fully demagnetized, the Drain voltage
evolution from the plateau level down to the V IN asymptote
is governed by the resonating energy transfer between the
L P transformer inductor and the global capacitance present
on the Drain. These voltage oscillations create current
oscillation in the parasitic capacitor across the switching
MOSFET (modelized by the Crss capacitance between
Gate and Drain): a negative current (flowing out of DRV
pin) takes place during the decreasing part of the Drain
oscillation, and a positive current (entering into the DRV
pin) during the increasing part.
The Drain valley corresponds to the inversion of the
current (i.e., the zero crossing): by detecting this point, we
always ensure a true valley turn ? on.
Isoxy
Crss
Lprim
Vswitch
T SWING
DRV
t
Figure 6. Soxyless Concept
Tswing + 0.5 Fres + p * Lp * Cdrain
The current in the Power MOSFET gate is:
Igate = Vringing/Zc (with Zc the capacitance impedance)
so
Igate = Vringing S (2 S p S Fres S Crss)
The magnitude of this gate current depends on the
MOSFET, the resonating frequency and the voltage swing
present on the Drain at the end of the plateau voltage.
The dead time T SWING is given by the equation:
(eq. 1)
(where L P is the primary transformer inductance and
C DRAIN the total capacitance present on the MOSFET
Drain. This capacitance includes the snubber capacitor if
any, the transformer windings stray capacitance plus the
parasitic MOSFET capacitances C OSS and C RSS ).
Internal Feedback Circuitry
To simplify the implementation of a primary regulation,
it is necessary to inject a current into the FB pin (instead of
sourcing it out). But to have a precise primary regulation,
the voltage present on FB pin must be regulated. Figure 8
gives the FB pin internal implementation: the circuitry
combines the functions of a current to voltage converter
and a voltage regulator.
Vdd
FB
+
3V
+
-
Internal
Setpoint
20 kHz
Low ? pass Filter
Figure 7. Internal Implementation of FB Pin
http://onsemi.com
11
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