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参数资料
| 型号： | NCP1351CPG |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM PROG CM OTP 8DIP |
| 标准包装： | 50 |
| 输出隔离： | 隔离 |
| 频率范围： | 调节 |
| 输入电压： | 9.5 V ~ 28 V |
| 工作温度： | -25°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
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NCP1351
APPLICATION INFORMATION
Roffset +
+
+ 3.7 k W
270 m
The Negative Sensing Technique
Standard current-mode controllers use the positive
sensing technique as portrayed by Figure 6. In this
technique, the controller detects a positive voltage drop
across the sense resistor, representative of the flowing
current. Unfortunately, this solution suffers from the
following drawbacks:
1. Difficulties to precisely adjust the peak current. If
1 V is the maximum sense level, you must
combine low valued resistors to reach the exact
limit you need.
2. The voltage developed across the sense resistor
subtracts from the gate voltage. If your VCC (min)
is 7 V, then the actual gate voltage at the end of the
current increases. When the result reaches the threshold
voltage (around 20 mV), the comparator toggles and resets
the main latch. Figure 3 details how the voltage moves on the
CS pin on a 1351 demoboard, whereas Figure 9 zooms on
the sense resistor voltage captured by respect to the
controller ground.
The choice of these two elements is simple. Suppose you
want to develop 1 V across the sense resistor. You would
select the offset resistor via the following formula:
1 1
(eq. 1)
ICS
If you need a peak current of 2 A, then, simply apply the
ohm law to obtain the sense resistor value:
on time, assuming a full load condition, is 7 V –
1 V = 6 V.
Rsense +
1
Ipeak_max
+
1
2
+ 0.5 W
(eq. 2)
3. The current in the sense resistor also includes the
C iss current at turn-on. This narrow spike often
disturbs the controller and requires adequate
treatment through a LEB circuitry for instance.
Figure 7 represents the negative current sense technique.
In this simplified example, the source directly connects to
the controller ground. Hence, if V CC is 8 V, the effective
gate-source voltage is very close to 8 V: no sense resistor
drop. How does the controller detect a negative excursion?
Due to the circuit flexibility, suppose you only have access
to a 0.33 W resistor. In that case, the peak current will exceed
the 2 A limit. Why not changing the offset resistor value
then? To obtain 2 A from the 0.33 W resistor, you should
develop:
The offset resistor is thus derived by:
Vsense + RsenseIpeak_max + 0.33 2 + 660 mV
(eq. 3)
In lack of primary current, the voltage on the CS pin reaches
R offset x I CS . Let us assume that these elements lead to have
1 V on this pin. Now, when the power MOSFET activates,
Roffset +
0.66
ICS
+
0.66
270 m
+ 2.44 k W
(eq. 4)
the current flows via the sense resistor and develop a
negative voltage by respect to the controller ground. The
voltage seen on the CS is nothing else than a positive voltage
(R offset x I CS ) plus the voltage across the sense resistor which
is negative. Thus, the CS pin voltage goes low as the primary
If reducing the sense resistor is of good practice to
improve the efficiency, we recommend to adopt sense values
between 0.5 V and 1 V. Reducing the voltage below these
levels will degrade the noise immunity.
+
I Lp
DRV
L P
+
V DD
DRV
L P
C Bulk
CS
V gs
I Lp
C Bulk
CS
ICS
-
Reset GND
I Lp
I Lp
Reset
I Lp
+
-
Peak
Setpoint R sense
GND
V sense
I Lp
V offset
R offset
+
+
V th
I Lp
V sense
Figure 6. Positive Current-Sense Technique
Figure 7. A Simplified Circuit of the Negative Sense
Implementation
http://onsemi.com
10
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