参数资料
| 型号： | NCP1392DDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/21页 |
| 文件大小： | 0K |
| 描述： | IC HALF BRIDGE DVR HV OSC 8SOIC |
| 标准包装： | 2,500 |
| 系列： | * |
NCP1392B, NCP1392D
APPLICATION INFORMATION
The NCP1392 is primarily intended to drive low cost half
bridge applications and especially resonant half bridge
applications. The IC includes several features that help the
designer to cope with resonant SPMS design. All features
are described thereafter:
? Wide Operating Frequency Range : The internal
current controlled oscillator is capable to operate over
wide frequency range. Minimum frequency accuracy is
$ 3%.
? Fixed Dead ? Time : The internal dead ? time helping to
fight with cross conduction between the upper and
lower power transistors. Three versions with different
dead time values are available to cover wide range of
applications.
? PFC Timer : Fixed delay is placed to IC operation
whenever the driver restarts (VCC ON or BO_OK detect
events). This delay assures that the bulk voltage will be
stabilized in the time the driver provides pulses on the
outputs. Another benefit of this delay is that the soft
start capacitor will be full discharged before any restart.
? Brown ? Out Detection : The BO input monitors bulk
voltage level via resistor divider and thus assures that
the application is working only for wanted bulk voltage
band. The BO input sinks current of 18.2 m A until the
Vref BO threshold is reached. Designer can thus adjust
the bulk voltage hysteresis according to the application
needs.
V DD
? Non ? Latched Enable Input : The enable comparator
input is connected in parallel to the BO terminal to
allow the designer stop the output drivers when needed.
There is no PFC delay when enable input is released so
skip mode for resonant SMPS applications and
dimming for light ballast applications are possible.
? Internal V CC Clamp : The internal zener clamp offers
a way to prepare passive voltage regulator to maintain
V CC voltage at 16 V in case the controller is supplied
from unregulated power supply or from bulk capacitor.
? Low Startup Current : This device features maximum
startup current of 50 m A which allows the designer to
use high value startup resistor for applications when
driver is supplied from the auxiliary winding. Power
dissipation of startup resistor is thus significantly
reduced.
Current Controlled Oscillator
The current controlled oscillator features a high ? speed
circuitry allowing operation from 50 kHz up to 960 kHz.
However, as a division by two internally creates the two Q
and Q outputs, the final effective signal on output Mlower
and Mupper switches in half frequency range. The VCO is
configured in such a way that if the current that flows out
from the Rt pin increases, the switching frequency also goes
up. Figure 28 shows the architecture of this oscillator.
S
D
Q
A
R soft ? start R t
+
?
+
?
V ref Rt
C t
I DT
+
?
V ref
+
?
CLK
R
Q
B
Dead
Time
C soft ? start
R t
Delay
From PFC Delay
PON
Reset
Figure 28. The Internal Current Controlled Oscillator Architecture
From EN
Cmp.
The internal timing capacitor Ct is charged by current
which is proportional to the current flowing out from the
Rt pin. The discharging current I DT is applied when voltage
on this capacitor reaches 2.5 V. The output drivers are
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. The charging
current and thus also whole oscillator is disabled during the
PFC delay period to keep the IC consumption below 400 m A.
http://onsemi.com
12
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