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参数资料
| 型号： | NCP1587ADR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 220kHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP1587, NCP1587A
FAULT
UVLO
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V CC is too low to
support the internal rails and power the converter. For the
NCP1587/A, the UVLO is set to permit operation when
converting from a 5.0 input voltage.
Overcurrent Threshold Setting
NCP1587/A can easily program an Overcurrent
Threshold ranging from 50 mV to 550 mV, simply by adding
a resistor (RSET) between BG and GND. During a short
period of time following V CC rising over UVLO threshold,
an internal 10 m A current (I OCSET ) is sourced from BG pin,
determining a voltage drop across R OCSET . This voltage
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
go through a Power On Reset (POR) cycle to reset the OCP
fault.
Drivers
The NCP1587 and NCP1587A include gate drivers to
switch external N ? channel MOSFETs. This allows the
devices to address high ? power as well as low ? power
conversion requirements. The gate drivers also include
adaptive non ? overlap circuitry. The non ? overlap circuitry
increase efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time.
A detailed block diagram of the non ? overlap and gate
drive circuitry used in the chip is shown in Figure 9.
1 BST
time length is about 6 ms. Connecting a R OCSET resistor
between BG and GND, the programmed threshold will be:
2
TG
IOCth + OCSET
I @ ROCSET
RDS(on)
(eq. 1)
RSET values range from 5 k W to 55 k W . In case R OCSET
is not connected, the device switches the OCP threshold to
a fixed 375 mV value: an internal safety clamp on BG is
triggered as soon as BG voltage reaches 700 mV, enabling
+
-
2V
8
PHASE
the 375 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ± 25 mV. The accuracy
of the set point is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
Current Limit Protection
In case of a short circuit or overload, the low ? side (LS)
FET will conduct large currents. The controller will shut
FAULT
+
-
V CC
4
3
BG
R set
GND
down the regulator in this situation for protection against
overcurrent. The low ? side R DS(on) sense is implemented at
the end of each of the LS ? FET turn ? on duration to sense the
over current trip point. While the LS driver is on, the Phase
voltage is compared to the internally generated OCP trip
voltage. If the phase voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter is initiated.
When the counter completes, the PWM logic and both
HS ? FET and LS ? FET are turned off. The controller has to
Figure 9. Block Diagram
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between V CC and GND and between BST
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
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| NCP1589AMNTWG | 功能描述:电压模式 PWM 控制器 BUCK REGULATOR RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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