参数资料
型号: NCP1592PAR2G
厂商: ON Semiconductor
文件页数: 3/20页
文件大小: 0K
描述: IC REG BUCK ADJ 6A 28TSSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.891 V ~ 5.4 V
输入电压: 3 V ~ 6 V
PWM 型: 电压模式
频率 - 开关: 330kHz ~ 700kHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
包装: *
供应商设备封装: *
NCP1592
AGND
VSENSE
COMP
PWRGD
BOOT
PH
1
2
3
4
5
6
28
27
26
25
24
23
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
7
8
9
10
11
12
13
14
Thermal
PAD
22
21
20
19
18
17
16
15
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
(Top View)
Figure 4. Pin Connections
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6 ~ 14
15 ~ 19
20 ~ 24
25
26
27
28
Symbol
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PGND
VIN
VBIAS
SS/ENA
SYNC
RT
Description
Analog ground. Return for compensation network/output divider, slow ? start capacitor. VBIAS capacitor, RT
resistor, and SYNC pin. Connect PowerPAD to AGND.
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
Power good open drain output. High when VSENSE ≥ 90% V ref otherwise PWRGD is low. Note that output is
low when SS/ENA is low or the internal shutdown signal is active.
Bootstrap output. 0.022 m F ~ 0.1 m F ceramic capacitor is recommended to connect between BOOT and PH
generates floating drive for the high ? side FET drive.
Phase output. Junction of the internal high ? side and low ? side power MOSFETs, and output inductor.
Power ground. High current return for the low ? side driver and power MOSFET. Connect PGND with large
copper areas to the input and output supply returns, and negative terminals of the input and output capacitors.
A single point connection to AGND is recommended.
Input supply for the power MOSFET switches and internal bias regulator . Bypass VIN pins to PGND with X5R
or higher quality 10 m F ceramic capacitors.
Internal bias voltage output. 0.1 m F ~ 1.0 m F low ESR ceramic capacitor is recommended to connect between
VBIAS to AGND.
Soft start/enable input/output. Dual function pin which provides logic input to enable/disable device operation
and capacitor input to externally set the start ? up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or
pin select between two internally set switching frequencies. When used to synchronize to an external signal, a
resistor must be connected to the RT pin.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When
using the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
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