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| 型号： | NCP1601APG |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/19页 |
| 文件大小： | 257K |
| 描述： | IC PFC CTRLR CRM/TRANSITION 8DIP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 Product Obsolescence 01/Jul/2009 |
| 标准包装： | 50 |
| 模式： | 临界传导（CRM），间歇式（转换） |
| 频率 - 开关： | 58kHz |
| 电流 - 启动： | 17µA |
| 电源电压： | 12.5 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 其它名称： | NCP1601APGOS |
NCP1601A, NCP1601B
http://onsemi.com
15
There is an internal capacitance C
osc(int)
(36 pF typical)
in the oscillator pin and the oscillator frequency is to
f
osc(max)
(405 kHz typical) when the Osc pin is opened.
Hence, the oscillator switching frequency can be
formulated in (eq.18) and represented in Figure 38.
(eq.18)
C
osc
=
36 pF ?405 kHz
f
osc
36 pF
0
100
200
300
400
500
600
700
0
50
100
150
200
f
osc
, Oscillator Frequency (kHz)
Figure 38. Osc Pin Frequency Setting
Synchronization Mode
The Osc pin (Pin 5) receives an external digital signal
with level high defined to be higher than V
sync(H)
(5 V
typical) and level low defined to be lower than V
sync(L)
(3.5 V typical). An internal 9 V ESD Zener diode is
connected to the Osc pin and hence the maximum
synchronization voltage is 9 V. The circuit recognizes a
synchronization frequency by the time difference between
two falling edge instants when the synchronization signal
across the 3.5 V threshold points. The actual
synchronizationthresholdpointisaslightlyhigherthanthe
3.5Vthresholdpoint.Theminimumsynchronizationpulse
width is 500 ns.
There is a typical 350 ns propagation delay from
synchronizationthresholdpointtothe momentofoutputgoes
highandthere isalsoa typical300nspropagationdelayfrom
thesynchronizationthresholdpointtothemomentofcrossing
3.5 V. Hence, the output goes high apparently when the sync
signal turns to 3.5 V. A timing diagram of synchronization
mode is summarized in Figure 39.
Figure 39. Synchronization Mode Timing Diagram in
DCM
Sync Signal
Osc Clock
Clock Edge
Drive Output
(DCM)
5 V
3.5 V
V
CC
Undervoltage Lockout (UVLO)
TherearetwoUVLOoptions. Thedevice typicallystarts
to operate when the supply voltage V
CC
exceeds 13.75 V
forNCP1601Aand10.5VforNCP1601B.Itturnsoffwhen
the supply voltage V
CC
goes below 9 V. An 18 V internal
ESD Zener diode is connected to the V
CC
pin (Pin 8).
Hence, the operating range is 9 V to 18 V.
The 4.75 V UVLO hysteresis option of the NCP1601A
and14mAlowstartupcurrent make the self- -supplydesign
easier. The 1.5 V UVLO hysteresis option of NCP1601B
makes it more flexible to match with the second- -stage
PWM controller biasing V
CC
supply voltage.
Thermal Shutdown
An internal thermal circuitry disables the circuit gate
driveandthenkeepsthepowerswitchoffwhenthejunction
temperature exceeds 140癈. The output stage is then
enabled once the temperature drops below typically 95癈
(i.e., 45癈 hysteresis). The thermal shutdown is provided
topreventpossibledevice failuresthatcouldresultfroman
accidental overheating.
Output Drive
Theoutputstageofthedeviceisdesignedfordirectdrive
of power MOSFET. It is capable of up to - -500 mA and
+750 mA peak drive current and has a typical rise and fall
time of 53 and 32 ns with a 1.0 nF load.
Table 1. Power Factor Controller Test Data
V
in
(Vac)
P
in
(W)
V
out
(V)
I
out
(mA)
PF
THD (%)
Efficiency (%)
90
143.4
327
400
0.998
4
91.2
110
161.1
373
400
0.997
6
92.6
130
160.5
378
400
0.996
6
94.2
150
160.9
382
400
0.993
7
95.0
180
161.6
386
400
0.990
6
95.5
190
161.7
387
400
0.986
8
95.7
210
162.0
389
400
0.980
8
96.0
230
162.2
391
400
0.973
9
96.4
250
162.8
393
400
0.959
16
96.6
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