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| 型号： | NCP1605BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/32页 |
| 文件大小： | 745K |
| 描述： | IC POWER FACTOR CTLR ENH 16-SOIC |
| 标准包装： | 1 |
| 系列： | Soft-Skip™ |
| 模式： | 临界传导（CRM），间歇导电（DCM） |
| 频率 - 开关： | 250kHz |
| 电流 - 启动： | 12mA |
| 电源电压： | 10 V ~ 20 V |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 标准包装 |
| 其它名称： | NCP1605BDR2GOSDKR |
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NCP1605, NCP1605A, NCP1605B
http://onsemi.com
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time (ms)
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Figure 57. Input Voltage and Ontime vs Time (example with F
SW
= 100 kHz, Pin =150 W, V
AC
= 230 V, L = 200 mH)
Regulation Block and Low Output Voltage Detection
A transconductance error amplifier with access to the
inverting input and output is provided. It features a typical
transconductance gain of 200 mS and a maximum
capability of ?0 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and
monitored by the inverting input (feedback pin Pin 4).
The bias current is minimized (less than 500 nA) to allow
the use of a high impedance feedback network. The output
of the error amplifier is pinned out for external loop
compensation (Pin 3). Typically a capacitor in the range of
100 nF, is applied between Pin 3 and ground, to set the
regulation bandwidth below 20 Hz, as need in PFC
applications.
The swing of the error amplifier output is limited within
an accurate range:
" It is forced above a voltage drop (V
F
) by some circuitry.
" It is clamped not to exceed 3.0 V + the same V
F
voltage
drop.
Hence, V
Pin3
features a 3 V voltage swing. V
Pin3
is then
offset down by (V
F
) and divided by three before it connects
to the V
TON
processing block and the PWM section.
Finally, the output of the regulation is a signal ( V
REGUL
of the block diagram) that varies between 0 and 1 V.
V
ref
Figure 58. Regulation Block
FB
OFF
?0 mA
OVLflag1
2R
3 V
0.955*Vref
pfcOK
200 mA
R
Figure 59. Correspondence between V
CONTROL
and V
REGUL
1 V
0 V
V
F
V
REGUL
V
CONTROL
3 V + V
F
V
control
+
+
V
F
V
out
Low
Detect
V
F
Error
Amplifier
V
REGUL
+
-
+
-
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
undershoots. Overshoots are limited by the Overvoltage
Protection (see OVP section). To contain the undershoots, an
internal comparator monitors the feedback (V
Pin4
) and when
V
Pin4
is lower than 95.5% of its nominal value, it connects a
200 mA current source to speedup the charge of the
compensation capacitor (Cpin3). Finally, it is like if the
comparator multiplied the error amplifier gain by 10.
One must note that this circuitry for undershoots limitation,
is not enabled during the startup sequence of the PFC stage
but only once the converter has stabilized (that is when the
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