参数资料
型号: NCP3127ADR2G
厂商: ON Semiconductor
文件页数: 8/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 8SOIC
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 4.5 V ~ 13.2 V
PWM 型: 电压模式
频率 - 开关: 350kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 标准包装
供应商设备封装: 8-SOICN
其它名称: NCP3127ADR2GOSDKR
NCP3127
3.85 V
source of 10 m A (typ), which charges the external integrator
capacitor of the OTA. Figure 14 is a typical soft ? start
sequence. The sequence begins once V IN and V BST surpass
their UVLO thresholds and OCP programming is complete.
The current sourced out of the COMP pin continually
increases the voltage until regulation is reached. Once the
voltage reaches 400 mV logic is enabled. When the voltage
exceeds 900 mV, switching begins. Current is sourced out of
the COMP pin, placing the regulator into open loop
operation until 800 mV is sensed at the FB pin. Once
800 mV is sensed at the FB pin, open loop operation ends
and closed loop operation begins. In closed loop operation,
the OTA is capable of sourcing and sinking 120 m A.
4.2 V
VCC
I OCSET = Sourced current
I OCth = Current trip threshold
R DS(on) = On resistance of the low side MOSFET
R SET = Current set resistor
The R SET values range from 5 k W to 55 k W . If R SET is not
connected, the device switches the OCP threshold to a fixed
375 mV value (3.57 A), an internal safety clamp on ISET is
triggered as soon as ISET voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending the OCP setting
period. The current trip threshold tolerance is $ 25 mV. The
accuracy is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
MOSFET tolerances with temperature and input voltage
will vary the over current set threshold operating point. A
graph of the typical current limit set thresholds at 4.5 V and
12 V is shown in Figure 19.
COMP
VFB
0.9 V
4
3.5
BG
3
2.5
12 V
TG
BG Comparator
DAC Voltage
BG Comparator Output
50 mV
500 mV
2
1.5
5.0 V
1
Vout
UVLO
POR Current Soft ? Start Normal Operation
Delay Trip Set COMP
Delay
Figure 18. Soft ? Start Sequence
UVLO
0.5
0
5
10
15 20
R SET (k W )
25
30
Overcurrent Threshold Setting
NCP3127 overcurrent threshold can be set from 50 mV to
550 mV, by adding a resistor (R SET ) between ISET and
GND. During a short period of time following V IN rising
over UVLO threshold, an internal 10 m A current (I OCSET ) is
sourced from the ISET pin, creating a voltage drop across
R SET . The voltage drop is compared against a stepped
internal voltage ramp. Once the internal stepped voltage
reaches the R SET voltage, the value is stored internally until
power is cycled. The overall time length for the OC setting
procedure is approximately 9 ms. Connecting an R SET
resistor between ISET and GND, the programmed threshold
will be:
Figure 19. R SET Value for Output Current
Current Limit Protection
In case of an overload, the low ? side (LS) FET will
conduct large currents. The regulator will latch off,
protecting the load and MOSFETs from excessive heat and
damage. Low ? side R DS(on) sense is implemented at the end
of each LS ? FET turn ? on duration to sense the current.
While the low side MOSFET is on, the V SW voltage is
compared to the user set internally generated OCP trip
voltage. If the V SW voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter counts
consecutive current trips. If the counter reaches 7, the PWM
I OCth +
I OCSET * R SET
R DS(on)
3 2.0 A +
10 m A * 21 k W
105 m W
(eq. 1)
logic and both HS ? FET and LS ? FET are turned off. The
regulator has to go through a Power On Reset (POR) cycle
to reset the OCP fault as shown in Figure 20.
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