参数资料
| 型号： | NCP3218GMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU SYNC BUCK 7BIT 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ADP3212, NCP3218, NCP3218G
ELECTRICAL CHARACTERISTICS
V CC = PV CC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
V VID = V DAC = 1.2000 V, T A = ? 40 ° C to 100 ° C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positiv e sign.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOLTAGE CONTROL
VOLTAGE ERROR AMPLIFIER (VEAMP)
FB, LLINE Voltage Range (Note 2)
FB, LLINE Offset Voltage (Note 2)
LLINE Bias Current
FB Bias Current
V FB , V LLINE
V OSVEA
I LLINE
I FB
Relative to CSREF = VDAC
Relative to CSREF = VDAC
? 200
? 0.5
? 100
? 1.0
+200
+0.5
+100
+1.0
mV
mV
nA
m A
LLINE Positioning Accuracy
V FB ? V VID
Measured on FB relative to V VID ,
LLINE forced 80 mV below CSREF
? 77.5
? 80
? 82.5
mV
COMP Voltage Range (Note 2)
COMP Current
COMP Slew Rate
Gain Bandwidth (Note 2)
V COMP
I COMP
SR COMP
GBW
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
C COMP = 10 pF, CSREF = VDAC,
Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
Non ? inverting unit gain configuration,
R FB = 1 k W
0.85
? 0.75
6
15
? 20
20
4.0
V
mA
V/ m s
MHz
VID DAC VOLTAGE REFERENCE
VDAC Voltage Range (Note 2)
See VID table
0
1.5
V
VDAC Accuracy
VDAC Differential Non ? linearity
(Note 2)
VDAC Line Regulation
VDAC Boot Voltage
(ADP3212, NCP3218)
VDAC Boot Voltage (NCP3218G)
Soft ? Start Delay (Note 2)
Soft ? Start Time
Boot Delay
VDAC Slew Rate (Note 2)
V FB ? V VID
Δ V FB
V BOOTFB
V BOOTFB
t DSS
t SS
t BOOT
Measured on FB (includes offset),
relative to V VID
V VID = 1.2000 V to 1.5000 V,
T = ? 40 ° C to 100 ° C
V VID = 0.3000 V to 1.1875 V,
T = ? 40 ° C to 100 ° C
VCC = 4.75 V to 5.25 V
Measured during boot delay period
Measured during boot delay period
Measured from EN pos edge to
FB = 50 mV
Measured from FB = 50 mV to FB
settles to 1.1 V within 5%
Measured from FB settling to 1.1 V
within 5% to CLKEN neg edge
Soft ? Start
Non ? LSB VID step, DPRSLP = H,
Slow C4 Entry/Exit
? 8.5
? 7.5
? 1.0
0.02
1.100
987.5
200
1.4
60
0.0625
0.25
+8.5
+7.5
+1.0
mV
LSB
%
V
mV
m s
ms
m s
LSB/ m s
Non ? LSB VID step, DPRSLP = L,
Fast C4 Exit
LSB VID step, DVID transition
1.0
0.4
FBRTN Current
I FBRTN
? 90
? 200
m A
VOLTAGE MONITORING and PROTECTION
POWER GOOD
CSREF Undervoltage Threshold
CSREF Overvoltage Threshold
CSREF Crowbar Voltage
Threshold
V UVCSREF
V OVCSREF
V CBCSREF
Relative to nominal VDAC voltage
Relative to nominal VDAC voltage
Relative to FBRTN, V VID > 1.1 V
Relative to FBRTN, V VID ≤ 1.1 V
? 240
150
1.5
1.3
? 300
200
1.55
1.35
? 360
250
1.6
1.4
mV
mV
V
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Guaranteed by design or bench characterization, not production tested.
Based on bench characterization data.
Timing is referenced to the 90% and 10% points, unless otherwise noted.
http://onsemi.com
5
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