参数资料
型号: NCP360SNT1G
厂商: ON Semiconductor
文件页数: 9/13页
文件大小: 0K
描述: IC CTLR USB POS OVP FET 5TSOP
标准包装: 1
电压 - 工作: 1.2 ~ 20V
电压 - 箝位: 7.4V
技术: 混合技术
电路数: 1
应用: USB
封装/外壳: 6-TSOP(0.059",1.50mm 宽)5 引线
供应商设备封装: 5-TSOP
包装: 标准包装
产品目录页面: 1127 (CN2011-ZH PDF)
其它名称: NCP360SNT1GOSDKR
NCP360, NCV360
In Operation
NCP360 provides overvoltage protection for positive
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the V out pin, against positive
over ? voltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built ? in undervoltage lock out (UVLO)
circuit. During V in positive going slope, the output remains
disconnected from input until V in voltage is above 3.2 V
nominal. The FLAGV output is pulled to low as long as V in
does not reach UVLO threshold. This circuit has a UVLO
hysteresis to provide noise immunity to transient condition.
V in (V)
20 V
OVLO
UVLO
0
V out
OVLO
UVLO
0
Figure 18. Output Characteristic vs. V in
Overvoltage Lockout (OVLO)
To protect connected systems on V out pin from
overvoltage, the device has a built ? in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled until the input voltage exceeds OVLO ?
Hysteresis.
FLAG output is tied to low until V in is higher than
OVLO. This circuit has a OVLO hysteresis to provide noise
immunity to transient conditions .
FLAG Output
NCP360 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded When V in level recovers normal condition,
FLAG is held high. The pin is an open drain output, thus a
pull up resistor (typically 1 M W ? Minimum 10 k W ) must
be provided to V battery . FLAG pin is an open drain output.
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal PMOS FET
NCP360 includes an internal PMOS FET to protect the
systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
R DSon , during normal operation, will create low losses on
V out pin, characterized by V in versus V out dropout. (See
Figure 16).
ESD Tests
NCP360 fully support the IEC61000 ? 4 ? 2, level 4 (Input
pin, 1 m F mounted on board).
That means, in Air condition, V in has a ± 15 kV ESD
protected input. In Contact condition, V in has ± 8 kV ESD
protected input.
Please refer to Fig 19 to see the IEC 61000 ? 4 ? 2
electrostatic discharge waveform.
Figure 19.
PCB Recommendations
The NCP360 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
By increasing PCB area, the R q JA of the package can be
decreased, allowing higher charge current to fill the battery.
Taking into account that internal bondings (wires
between package and silicon) can handle up to 1 A (higher
than thermal capability), the following calculation shows
two different example of current capability, depending on
PCB area:
? With 305 ° C/W (without PCB area), allowing DC
current is 500 mA
? With 260 ° C/W (200 mm 2 ), the charge DC current
allows with a 85 ° C ambient temperature is:
I = √ (T J -T A )/(R q JA x R DSON )
I = 625 mA
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