参数资料
| 型号： | NCP4200MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/32页 |
| 文件大小： | 0K |
| 描述： | IC CONV SYNC BUCK PMBUS 40QFN |
| 标准包装： | 2,500 |
| 应用： | 转换器，Intel VR11，VR11.1 |
| 输入电压： | 1.7 V ~ 24 V |
| 输出数： | 1 |
| 输出电压： | 0.375 V ~ 1.8 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
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NCP4200
PIN FUNCTION DESCRIPTIONS
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 to 25
26 to 29
30
31 to 38
39
40
Mnemonic
VCC3
ALERT
FAULT
SDA
SCL
EN
GND
IMON
IREF
RT
RAMPADJ
TRDET
FBRTN
COMP
FB
CSREF
CSSUM
CSCOMP
ILIMITFS
ODN
OD1
SW4 to SW1
PWM4 to PWM1
VCC
VID7 to VID0
PSI
PWRGD
Description
3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval
3.3 V LDO.
ALERT Output. Open drain output that asserts low when the VR exceeds a programmable limit.
FAULT Output. Open drain output that asserts low when a fault has occurred. The fault can be due to
VR or current limit, crowbar, or undervoltage. The trip points are loaded into registers.
Digital Input/Output. I 2 C serial data bidirectional pin. Requires pullup.
Digital Input. I 2 C serial bus clock open drain input. Requires pullup.
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the
PWRGD output low.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Analog Filter Output. A capacitor from this pin to ground sets the default current monitor filter
frequency. The frequency can be modified using the serial interface.
Current Reference Input. An external resistor from this pin to ground sets the reference current for
IFB, IILIMITFS and ITH(X).
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the
internal PWM ramp.
Transient Detect.
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Error Amplifier Output and Compensation Point.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor
between this pin and the output voltage sets the no load offset point.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the
current sense amplifier and the power ? good and crowbar functions. This pin should be connected to
the common point of the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the average
inductor currents together to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the
gain of the current sense amplifier and the positioning loop response time.
Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal
current sensing signal for current limit and IMON. This value can be overwritten using the I 2 C
interface.
Output Disable Logic Output for phases 2 ? 4. This pin is actively pulled low when the EN input is low
or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high ? side and
low ? side outputs should go low.
Output Disable Logic Output for phase one. This pin is actively pulled low when the EN input is low
or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high ? side and
low ? side outputs should go low.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of
unused phases should be left open.
Logic ? Level PWM Outputs. Each output is connected to the input of an external MOSFET driver
such as the ADP3120A. Connecting the PWM4, and PWM3 outputs to VCC causes that phase to
turn off, allowing the NCP4200 to operate as a 2 ? phase controller.
Supply Voltage for the Device.
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if
left open. When in normal operation mode, the DAC output programs the FB regulation voltage from
0.375 V to 1.6 V.
Power Save Interface. System signal to select single phase option.
Power ? Good Output. Open ? drain output that signals when the output voltage is outside of the proper
operating range.
http://onsemi.com
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