参数资料
| 型号： | NCP5215MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/21页 |
| 文件大小： | 0K |
| 描述： | IC CTLR SYNC BUCK DUAL 40-QFN |
| 产品变化通告： | Product Discontinuation 01/Oct/2008 |
| 标准包装： | 2,500 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 4.5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
NCP5215
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
FSET
VCC
AGND
VREF
PGOOD1
PGOOD2
EN1
EN2
SS1
SS2
TRESET2
COMP2
INV2
FB2
VDRP2
ILMT2
CS2 ? / Vo2
CS2+
SWN2
TG2
BST2
VCCP2
BG2
PGND2
FPWM#
Vin
PGND1
BG1
VCCP1
BST1
TG1
SWN1
CS1+
CS1 ? / Vo1
ILMT1
VDRP1
FB1
INV1
COMP1
TRESET1
Description
Frequency SET Programmable pin of switching frequency for two channels.
VCC This pin powers the control section of IC.
Analog Ground Low noise ground for control section of IC.
Reference Voltage Output Internal 0.8 V reference output.
Power GOOD 1 Power good indicator of the output voltage of Channel 1. (Open drained)
Power GOOD 2 Power good indicator of the output voltage of Channel 2. (Open drained)
Enable 1 Enable logic input of Channel 1.
Enable 2 Enable logic input of Channel 2.
Soft ? Start 1 Soft ? starting programmable pin of Channel 1.
Soft Start 2 Soft ? starting programmable pin of Channel 2.
Transient Response Enhancement SET 2 Channel 2 Transient ? Response ? Enhancement (TRE)
programmable pin.
COMP2 Output of the error amplifier of Channel 2.
Inverting Input 2 Error amplifier’s inverting input pin of Channel 2.
Feedback 2 Output voltage feedback of Channel 2.
Voltage Droop 2 Channel 2 voltage droop output to the compensation. This pin is used to program the
adaptive ? voltage ? position (AVP) function for Channel 2.
Current Limit 2 Current limit programmable pin of Channel 2.
Current Sense 2 ? Channel 2 inductor current differential sense inverting input.
Current Sense 2+ Channel 2 inductor current differential sense non ? inverting input.
Switch Node 2 Switch node between the top MOSFET and bottom MOSFET of Channel 2.
Top Gate 2 Gate driver output of the top N ? Channel MOSFET for Channel 2.
BOOTSTRAP Connection 2 Channel 2 top gate driver input supply, a bootstrap capacitor connection
between SWN2 and this pin.
VCC Power 2 This pin powers the bottom gate driver of Channel 2.
Bottom Gate 2 Gate driver output of the bottom N ? Channel MOSFET for Channel 2.
Power Ground 2 Ground reference and high ? current return path for the bottom gate driver of Channel 2.
Forced PWM Forced PWM enable logic input. Low to enable forced PWM mode and disable power ? saving
mode for both channels.
Vin Input voltage monitor input.
Power Ground 1 Ground reference and high ? current return path for the bottom gate driver of Channel 1.
Bottom Gate 1 Gate driver output of the bottom N ? Channel MOSFET for Channel 1.
VCC Power 1 This pin powers the bottom gate driver of Channel 1.
BOOTSTRAP Connection 1 Channel 1 top gate driver input supply, a bootstrap capacitor connection
between SWN1 and this pin.
Top Gate 1 Gate driver output of the top N ? Channel MOSFET for Channel 1.
Switch Node 1 Switch node between the top MOSFET and bottom MOSFET of Channel 1.
Current Sense 1+ Channel 1 inductor current differential sense non ? inverting input.
Current Sense 1 ? Channel 1 inductor current differential sense inverting input.
Current Limit 1 Current limit programmable pin of Channel 1.
Voltage Droop 1 Channel 1 voltage droop output to the compensation. This pin is used to program the
Adaptive ? Voltage ? Position (AVP) function for Channel 1.
Feedback 1 Output voltage feedback of Channel 1.
Inverting Input 1 Error amplifier’s inverting input pin of Channel 1.
COMP1 Output of the error amplifier of Channel 1.
Transient Response Enhancement SET 1 Channel 1 Transient ? Response ? Enhancement (TRE)
program pin.
http://onsemi.com
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