参数资料
| 型号： | NCP5252MNTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2A 16QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 4.5 V ~ 13.2 V |
| 频率 - 开关： | 333kHz ~ 1MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-QFN（3x3） |
| 其它名称： | NCP5252MNTXGOSDKR |
NCP5252
ELECTRICAL CHARACTERISTICS (V CC = 4.5 to 13.2 V, T A = ? 40 ° C to 85 ° C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
SWITCHING MODULATOR
Minimum T on
Minimum T off
PWM Comparator Offset
Propagation Delay of PWM
Comparator
T on_min
T off_min
TD_PWM
(Note 1)
(Note 1)
(Note 1)
(Note 1)
40
200
50
225
5.0
60
250
10
20
ns
ns
mV
ns
VOLTAGE ERROR AMPLIFIER
DC Gain
Open ? Loop Phase Margin
Unity Gain Bandwidth
Slew Rate
FB Bias Current
Output Voltage Swing
GAIN_VEA
PH_EA
BW_VEA
SR_VEA
I bias_FB
V max_EA
V min_EA
(Note 1)
(Note 1)
(Note 1)
COMP PIN TO GND = 100 pF
(Note 1)
I source_EA = 2mA
I sink_EA = 2mA
80
50
15
5.0
3.3
88
20
3.5
0.15
0.1
0.3
dB
Deg
MHz
V/ m s
m A
V
V
OVERCURRENT PROTECTION LIMIT
High Side Peak Current Limit
(Cycle ? by ? Cycle)
Low Side Valley Current Limit,
Short ? Circuit (4 m s)
Low Side Valley Current Limit
(Current Limit, 16 m s)
HSOC
LSOC_S
LSOC_L
T on Minimum > 100 ns
(Notes 1 & 2)
(Notes 1 & 2)
(Notes 1 & 2)
3.4
3.0
2.0
4.0
3.75
2.5
4.6
4.5
3.4
A
A
A
POWER OUTPUT SECTION
Internal Main FET ON ? Resistance
Internal Sync FET ON ? Resistance
LX Leakage Current
R DS(on)_M
R DS(on)_F
LX_LK
(I LX =100mA, VBST ? LX = 5 V,
FB = 0, T A = 25 ° C) (Note 1)
(I LX = 100 mA, FB = 1 V, T A = 25 ° C)
(Note 1)
V EN = 0V, LX = 0, V CC = 13.2 V
150
100
225
150
+5.0
m W
m W
m A
CONTROL SECTION
LX = 13.2, V CC = 13.2 V
? 5.0
m A
EN / SKIP Logic Input Voltage for
Disable
EN / SKIP Logic Input Voltage for
FPWM
EN / SKIP Logic Input Voltage for
Skip Mode
EN / SKIP Source Current
EN / SKIP Sink Current
V EN_DISABLE
V EN_HYS
V EN_FPWM
V EN_SKIP
V EN_HYS
I EN_SOURCE
I EN_SINK
Set as Disable
Hysteresis
Set as FCCM mode
Set as SKIP Mode
Hysteresis
V EN_SKIP = 0 V
V EN_SKIP = 5 V
0.7
1.7
2.25
1.0
300
1.95
2.45
250
1.3
2.10
2.65
0.1
0.1
V
mV
V
V
mV
m A
m A
EN_SKIP Logic Input Delay
Change mode delay active
3
Clk
PGOOD Pin ON Resistance
PGOOD Pin OFF Current
PGOOD_R
PGOOD_LK
I_PGOOD = 5 mA
PGOOD = 5 V
75
1
W
m A
OUTPUT DISCHARGE MODE
Output Discharge On ? Resistance
R discharge
EN = 0 V
20
35
W
THERMAL SHUTDOWN
Thermal Shutdown
Thermal Shutdown Hysteresis
T sd
T sdhys
(Note 1)
(Note 1)
150
25
° C
° C
1. Guaranteed by design, not tested in production.
2. Test mode disables the T on /T off min.
http://onsemi.com
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