参数资料
| 型号： | NCP5378MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 1PH SYNC BUCK 32QFN |
| 标准包装： | 3,000 |
| 应用： | 控制器，用于下一代 Intel 处理器的电源 |
| 输入电压： | 4.3 V ~ 7 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
NCP5378
ELECTRICAL CHARACTERISTICS
0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 4.75 < V CC < 5.25 V; All DAC Codes; C VCC = 0.1 m F unless otherwise noted.
Parameter
Test Conditions
Min
Typ
Max
Unit
VDROOP AMPLIFIER
Open Loop Phase Margin
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
C L = 20 pF to GND including ESD
R L = 1 k W to GND
C L = 20 pF to GND including ESD
R L = 1 k W to GND
10 mV of Overdrive, I SOURCE = 4.0 mA
10 mV of Overdrive, I SINK = 1.0 mA
10 mV of Overdrive, V out = 3.0 V
10 mV of Overdrive, V out = 1.0 V
?
?
3.0
?
4.0
1.0
70
10
?
?
?
?
?
?
?
1.0
?
?
°
V/ m s
V
V
mA
mA
CSSUM AMPLIFIER
Current Sense Input to V DRP ? 3 dB Bandwidth
Current Summing Amp Output Offset Voltage
Maximum CSSUM Output Voltage
Minimum CSSUM Output Voltage
Output Source Current
Output Sink Current
C L = 10 pF to GND,
R L = 10 k W to GND
CSP ? CSN = 0, CSP = 1.1 V
CSP ? CSN = ? 0.2 V
(all phases) I SOURCE = 1 mA
CSP ? CSN = 0.7 V
(all phases) I SINK = 1 mA
V out = 3.0 V
V out = 0.3 V
?
? 16
3.0
?
1.0
4.0
12
?
?
?
?
?
?
+5
?
0.3
?
?
MHz
mV
V
V
mA
mA
CURRENT SENSE AMPLIFIERS
Input Bias Current
Common Mode Input Voltage Range
Differential Mode Input Voltage Range
Current Sharing Offset CSP to CSN (Note 3)
Current Sense Input to CSSUM Gain
CSP = CSN = 1.4 V
all VIOS
0 V < CSP ? CSN < 0.1 V
? 50
? 0.3
? 120
? 2
? 3.834
?
?
?
?
? 3.7
50
2.0
120
2
? 3.574
nA
V
mV
mV
V/V
IMON
V DRP to IMON Gain
Current Sense Input to V DRP ? 3 dB Bandwidth
Output Referred Offset Voltage
Minimum Output Voltage
Maximum Output Voltage
Output Sink Current
Maximum Clamp Voltage
1.325 V > V DRP > 1.75 V
C L = 30 pF to GND,
R L = 100 k W to GND
V DRP = 1.5 V, I SOURCE = 0 mA
V DRP = 1.3 V, I SINK = 25 m A
I out = 300 m A
V out = 0.3 V
IMON ? VSN V DRP = HIGH
R LOAD = Open
1.965
?
0
?
1.0
175
1.1
?
4.0
23
?
?
?
?
2.02
?
50
0.1
?
?
1.2
V/V
MHz
mV
V
V
m A
V
RPM THRESHOLD
Ramp Slope (Note 3)
R OSC = 69.8 k W , DAC = 1.1 V
0.175
V/ m s
R OSC Output
1.93
2.00
2.05
V
VR_RDY (Power Good) OUTPUT
VR_RDY Output Saturation Voltage
VR_RDY Rise Time
I PGD = 5 mA
External pull ? up of 1 K W to 1.25 V,
C TOT = 45 pF, D Vo = 10% to 90%
?
?
?
100
0.4
250
V
ns
3. Guaranteed by design.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
http://onsemi.com
6
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