参数资料
型号: NCP5391MNR2G
厂商: ON Semiconductor
文件页数: 20/26页
文件大小: 0K
描述: IC CTLR BUCK 2/3PHASE 32-QFN
产品变化通告: Product Discontinuation 30/Sept/2011
标准包装: 1
应用: 控制器,Intel Pentium? IV
输入电压: 10.8 V ~ 13.2 V
输出数: 3
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 剪切带 (CT)
其它名称: NCP5391MNR2GOSCT
NCP5391
Dynamic VID Testing
The VTT tool provides for VID stepping based on the
Intel Requirements. Select the Dynamic VID option.
Before enabling the test set the lowest VID to 0.5 V or
greater and set the highest VID to a value that is greater than
the lowest VID selection, then enable the test. See Figures
10 through 12.
Design Methodology
Decoupling the V CC Pin on the IC
An RC input filter is required as shown in the V CC pin to
minimize supply noise on the IC. The resistor should be
sized such that it does not generate a large voltage drop
between the 12 V supply and the IC. See the schematic
values.
Understanding Soft-Start
The controller will ramp to the 1.1 V, with a pause to
capture the VID code then resume ramping to target value
based on an internal slew rate limit. See Figure 13. The
controller is designed to regulate to the voltage on the SS
pin until it reaches the internal DAC voltage. The soft-start
cap sets the initial ramp rate using a typical 5.0 m A current.
The typical value to use for the soft-start cap (SS), is
typically set to 0.01 m F. This results in a ramp time to 1.1 V
of 2.2 ms based on equation 1.
Css ^ iss
dtss
dvss
1.1 · V + dvss and i ss + 5 · m A
Figure 10. 1.6 to 0.5 Dynamic VID Response
2.2 · ms dtss
(eq. 1)
Css + 0.01 · m F
Figure 11. Dynamic VID Settling Time Rising
Figure 13. VR11 Startup
Figure 12. Dynamic VID Settling Time Falling
http://onsemi.com
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