参数资料
型号: NCP5395GMNR2G
厂商: ON Semiconductor
文件页数: 10/29页
文件大小: 0K
描述: IC PHASE CONTROLLER 2/3/4 48-QFN
标准包装: 2,500
应用: 控制器,Intel VR11
输入电压: 4.75 V ~ 5.25 V
输出数: 4
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
NCP5395
ELECTRICAL CHARACTERISTICS
0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 4.75 < V CC < 5.25 V; All DAC Codes; C VCC = 0.1 m F unless otherwise noted.
Parameter
Test Conditions
Min
Typ
Max
Unit
CURRENT SENSE AMPLIFIERS
Input Bias Current
Common Mode Input Voltage Range
Differential Mode Input Voltage Range
Current Sharing Output Voltage
Current Sense Input to PWM Gain
Current Sense Input to CSSUM Gain
CSx = CSxN = 1.4 V
CSx = CSxN = 1.00 V,
0 V < CSx ? CSxN < 0.1 V,
0 V < CSx ? CSxN < 0.1 V
? 50
? 0.3
? 120
? TBD
5.4
? 3.793
?
?
?
?
5.7
? 3.7
50
2.0
120
TBD
6.0
? 3.608
nA
V
mV
mV
V/V
V/V
IMON
V DRP to IMON Gain
Current Sense Input to V DRP ? 3 dB Bandwidth
V DRP to IMON Output Slew Rate
Output Referred Offset Voltage
Minimum Output Voltage
Maximum Output Voltage
Output Sink Current
Maximum Clamp Voltage
1.325 V > V DRP > 1.75 V
C L = 30 pF to GND,
R L = 100 k W to GND
C L = 30 pF to GND,
Load = 100k to GND
V DRP = 1.5 V, I SOURCE = 0 mA
V DRP = 1.3 V, I SINK = 25 m A
I out = 300 m A
V out = 0.3 V
IMON ? VSN V DRP = HIGH
R LOAD = Open
1.89
?
?
? TBD
?
1.0
175
1.1
2.0
4.0
TBD
?
?
?
?
?
2.02
?
?
TBD
0.1
?
?
1.15
V/V
MHz
V/ m s
mV
V
V
m A
V
OSCILLATOR
Switching Frequency Range
100
?
1100
kHz
Switching Frequency Accuracy
Switching Frequency Accuracy
Switching Frequency Accuracy (2ph or 4ph)
Switching Frequency Accuracy (3ph)
ROSC Output Voltage
200 kHz < F SW < 600 kHz
100 kHz < F SW < 1 MHz
R OSC = 69.8k
R OSC = 16.2k
R OSC = 7.5k
R OSC = 69.8k
R OSC = 16.2k
R OSC = 7.5k
?
?
TBD
475
TBD
TBD
494
TBD
1.93
?
?
?
?
?
?
?
?
2.00
5.0
10
TBD
525
TBD
TBD
546
TBD
2.05
%
%
kHz
kHz
V
MODULATORS (PWM Comparators)
Minimum Pulse Width
Magnitude of the PWM Ramp
0% Duty Cycle
100% Duty Cycle
PWM Phase Angle Error
Fsw = 800 kHz
COMP Voltage when the PWM
Outputs Remain LO
COMP Voltage when the PWM
Outputs Remain HI
Between Adjacent Phases
?
TBD
TBD
?
? TBD
30
1.0
150
1.15
?
?
TBD
TBD
?
TBD
ns
V
mV
V
°
VR_RDY (Power Good) OUTPUT
VR_RDY Output Saturation Voltage
I PGD = 10 mA
?
?
0.4
V
Design guaranteed.
For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
Guaranteed by design; not tested in production.
Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
No DAC offset is implemented for AMD operation.
http://onsemi.com
10
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