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| 型号： | NCP5424D |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 48 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
NCP5424
+ IN
PRMS(H) + IRMS(H)2 RDS(ON)
where:
P RMS(H) = switching MOSFET conduction losses;
I RMS(H) = maximum switching MOSFET RMS current;
R DS(ON) = FET drain?to?source on?resistance
The upper MOSFET switching losses are caused during
MOSFET switch?on and switch?off and can be determined
by using the following formula:
PSWH + PSWH(ON) ) PSWH(OFF)
V IOUT (tRISE ) tFALL)
6T
where:
P SWH(ON) = upper MOSFET switch?on losses;
P SWH(OFF) = upper MOSFET switch?off losses;
V IN = input voltage;
I OUT = load current;
t RISE = MOSFET rise time (from FET manufacturer ’s
switching characteristics performance curve);
t FALL = MOSFET fall time (from FET manufacturer ’s
switching characteristics performance curve);
T = 1/f SW = period.
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PSWL + VSD ILOAD non?overlap time fSW
where:
P SWL = lower FET switching losses;
V SD = lower FET source?to?drain voltage;
I LOAD = load current;
Non?overlap time = GATE(L)?to?GATE(H) or
GATE(H)?to?GATE(L) delay (from NCP5424 data sheet
Electrical Characteristics section);
f SW = switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL) + PRMS(L) ) PSWL
where:
P LFET(TOTAL) = Synchronous (lower) FET total losses;
P RMS(L) = Switch Conduction Losses;
P SWL = Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)
TJ + TA ) [PLFET(TOTAL)
where:
T J = MOSFET junction temperature;
R q JA]
where:
P HFET(TOTAL) = total switching (upper) MOSFET losses;
P RMS(H) = upper MOSFET switch conduction Losses;
P SWH(ON) = upper MOSFET switch?on losses;
P SWH(OFF) = upper MOSFET switch?off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
TJ + TA ) [PHFET(TOTAL) R q JA]
where:
T J = FET junction temperature;
T A = ambient temperature;
P HFET(TOTAL) = total switching (upper) FET losses;
R q JA = upper FET junction?to?ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
PRMS(L) + IRMS2 RDS(ON)
+ [IOUT (1 * D) ]2 RDS(ON)
where:
P RMS(L) = lower MOSFET conduction losses;
I OUT = load current;
D = Duty Cycle;
R DS(ON) = lower FET drain?to?source on?resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
T A = ambient temperature;
P LFET(TOTAL) = total synchronous (lower) FET losses;
R q JA = lower FET junction?to?ambient thermal resistance.
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V CC , and the NCP5424 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
PCONTROL(IC) + ICC1VCC1 ) IBSTVBST ) PGATE(H)1
) PGATE(L)1 ) PGATE(H)2 ) PGATE(L)2
where:
P CONTROL(IC) = control IC power dissipation;
I CC1 = IC quiescent supply current;
V CC1 = IC supply voltage;
P GATE(H) = upper MOSFET gate driver (IC) losses;
P GATE(L) = lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
PGATE(H) + QGATE(H) fSW VBST
where:
P GATE(H) = upper MOSFET gate driver (IC) losses;
Q GATE(H) = total upper MOSFET gate charge at V CC ;
f SW = switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
on into near zero voltage conditions. The MOSFET body
PGATE(L) + QGATE(L)
fSW
VCC
diode will conduct during the non?overlap time and the
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