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| 型号： | NCP5424DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 其它名称： | NCP5424DR2OSDKR |
NCP5424
MAXIMUM RATINGS
Operating Junction Temperature, T J
Storage Temperature Range, T S
ESD Susceptibility (Human Body Model)
Rating
Value
150
?65 to +150
2.0
Unit
° C
° C
kV
Package Thermal Resistance, SOIC?16:
Lead Temperature Soldering:
Junction?to?Case, R q JC
Junction?to?Ambient, R q JA
Reflow: (SMD styles only) (Note 1)
28
115
230 peak
° C/W
° C/W
° C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183 ° C.
MAXIMUM RATINGS
Pin Symbol
V CC
COMP1, COMP2
V FB1 , V FB+2 , V FB?2
BST
R OSC
GATE(H)1 ,
Pin Name
IC Power Input
Compensation Capacitor for Channel 1 or 2
Voltage Feedback Input for Channel 1 or 2
Power Input for GATE(H)1, 2
Oscillator Resistor
High?Side FET Driver for Channel 1 or 2
V MAX
16 V
4.0 V
5.0 V
20 V
4.0 V
20 V
V MIN
?0.3 V
?0.3 V
?0.3 V
?0.3 V
?0.3 V
?0.3 V
I SOURCE
N/A
1.0 mA
1.0 mA
N/A
1.0 mA
1.5 A peak, 200 mA DC
I SINK
1.5 A peak, 200 mA DC
3.5 mA
1.0 mA
1.5 A peak, 200 mA DC
1.0 mA
1.5 A peak, 200 mA DC
GATE(H)2
GATE(L)1 , GATE(L)2
GND
IS+1, IS+2
IS?
Low?Side FET Driver for Channel 1 or 2
Ground
Positive Current Sense for Channel 1 or 2
Negative Current Sense for Channels 1 and 2
16 V
0V
6.0 V
6.0 V
?0.3 V
0V
?0.3 V
?0.3 V
1.5 A peak, 200 mA DC
1.5 A peak, 200 mA DC
1.0 mA
1.0 mA
1.5 A peak, 200 mA DC
N/A
1.0 mA
1.0 mA
PACKAGE PIN DESCRIPTION
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS?
V FB1
COMP1
COMP2
V FB?2
V FB+2
IS+2
R OSC
V CC
GATE(L)2
GATE(H)2
FUNCTION
High Side Switch FET driver pin for channel 1.
Low Side Synchronous FET driver pin for channel 1.
Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
Power input for GATE(H)1 and GATE(H)2 pins.
Positive input for channel 1 overcurrent comparator.
Negative input for channels 1 and 2 overcurrent comparator.
Error amplifier inverting input for channel 1.
Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation.
The same capacitor provides Soft?Start timing for channel 1. This pin also disables the channel 1 output when pulled
below 0.3 V.
Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation
and Soft?Start timing for channel 2. Channel 2 output is disabled when this pin is pulled below 0.3 V.
Error amplifier inverting input for channel 2.
Error amplifier noninverting input for channel 2.
Positive input for channel 2 overcurrent comparator.
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
Input Power supply pin.
Low Side Synchronous FET driver pin for channel 2.
High Side Switch FET driver pin for channel 2.
http://onsemi.com
3
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