参数资料
| 型号： | NCP5424DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 21/Jan/2010 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5424DR2GOSCT |
NCP5424
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
D VESR + D IOUT ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
SELECTION OF THE POWER FET
FET Basics
The use of a MOSFET as a power switch is compelled by
two reasons: 1) high input impedance ; and 2) fast switching
times . The electrical characteristics of a MOSFET are
considered to be nearly those of a perfect switch. Control
ESLMAX +
D VESL
D I
D t
and drive circuitry power is therefore reduced. Because the
input impedance is so high, it is voltage driven. The input of
the MOSFET acts as if it were a small capacitor, which the
LIN +
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor ’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
The minimum inductance value for the input inductor is
therefore:
D V
(dI dt)MAX
where:
L IN = input inductor value;
D V = voltage seen by the input inductor during a full load
swing;
(dI/dt) MAX = maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double?pole network
with a slope of ?2.0, a roll?off rate of ?40 dB/dec, and a
corner frequency:
driving circuit must charge at turn on. The lower the drive
impedance, the higher the rate of rise of V GS , and the faster
the turn?on time. Power dissipation in the switching
MOSFET consists of 1) conduction losses, 2) leakage
losses, 3) turn?on switching losses, 4) turn?off switching
losses, and 5) gate?transitions losses. The latter three losses
are proportional to frequency.
The most important aspect of FET performance is the
Static Drain?To?Source On?Resistance (R DS(ON) ), which
affects regulator efficiency and FET thermal management
requirements. The On?Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On?Resistance also
increases. Its positive temperature coefficient is between
+0.6%/ ° C and +0.85%/ ° C. The higher the On?Resistance
the larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail?to?rail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
where:
L = input inductor;
fC +
2 p
1
LC
in the FET switch does not cause the power component’s
junction temperature to exceed 150 ° C.
The maximum RMS current through the switch can be
determined by the following formula:
C = input capacitor(s).
IRMS(H) +
IL(PEAK)2 ) (IL(PEAK)
) IL(VALLEY)2 D
3
IL(VALLEY))
where:
I RMS(H) = maximum switching MOSFET RMS current;
I L(PEAK) = inductor peak current;
I L(VALLEY) = inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
http://onsemi.com
12
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