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参数资料
| 型号： | NCP5424EVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/18页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP5424 |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 设计资源： | NCP5424 Demo Board BOM NCP5424EVB Gerber Files NCP5424EVB Schematic |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.5V |
| 电流 - 输出： | 17A |
| 输入电压： | 3.3V，5V，12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP5424 |
| 其它名称： | NCP5424EVBOS |
NCP5424
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
LAYOUT GUIDELINES
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the NCP5424.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
4. For high power buck regulators on double?sided
PCB’s a single ground plane (usually the bottom) is
recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, four?layer PCB’s are the
optimum approach to reducing susceptibility to
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Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
Place the switching MOSFET as close to the input
capacitors as possible.
Place the output capacitors as close to the load as
possible.
Place the COMP capacitor as close as possible to the
COMP pin.
Connect the filter components of the following pins:
R OSC, V FB , V OUT , and COMP to the GND pin with a
single trace, and connect this local GND trace to the
output capacitor GND.
Place the V CC bypass capacitors as close as possible
to the IC.
Place the R OSC resistor as close as possible to the
R OSC pin.
Include provisions for 100?100pF capacitor across
each resistor of the feedback network to improve
noise immunity and add COMP.
Assign the output with lower duty cycle to channel 2,
which has better noise immunity.
http://onsemi.com
17
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NCP5425 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Synchronous Buck Controller |
| NCP5425/D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Dual Synchronous Buck Controller |
| NCP5425_06 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Synchronous Buck Controller |
| NCP5425DB | 功能描述:DC/DC 开关控制器 Dual Synchronous RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5425DBG | 功能描述:DC/DC 开关控制器 Dual Synchronous Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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