参数资料
型号: NCP5425DBR2
厂商: ON Semiconductor
文件页数: 10/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20TSSOP
产品变化通告: Product Obsolescence 14/Apr/2010
标准包装: 2,500
PWM 型: 电压模式
输出数: 2
频率 - 最大: 938kHz
占空比: 100%
电源电压: 4.75 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 125°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)
其它名称: NCP5425DBR2OS
NCP5425
Current Sharing
When used in a two separate input to a single output mode,
the NCP5425 dual controller can provide input power
sharing in either of two ways:
? A preset ratio. For example, Channel 1 could provide
70% of the load current, and Channel 2, the remaining
30%. Practical ratios for Channel 1/Channel 2
contribution to total load current range from 50%?50%
to 80%?20%.
? A preset ratio up to a specific current contribution from
Channel 2. In excess of that limit, all of the additional
load current would be supplied by Channel 1. Figure 7
depicts the actual performance of a NCP5425
configured in a 70%?30% share ratio, with Channel 2
output current limited to 5.0 Amps.
The availability both Channel 2 error amplifier inputs
(signal and reference) at device pins is key to programmable
current ratio sharing. Current sense information from
Channel 1 is connected to the reference input of the Channel
2 error amplifier. Current information from Channel 2 is fed
back to the error amplifier’s inverting input. Channel 2 will
therefore act to adjust its current to match the current
information fed to its reference input from Channel 1. If this
information is one?half the voltage developed across the
Channel 1 output inductor, Channel 2 will run at half the
current and supply a approximately 33% of the total load
current. This application is illustrated in Figure 7.
In some applications the power supply designer may not
only wish to draw a known percentage of power from one
source, but also limit the power drawn from that source. The
current limit amplifier on Channel 2 can be programmed to
budget the maximum input power into Channel 2 and all
power in excess of that limit will be supplied solely by
Channel 1. This is accomplished by setting the Channel 2
cycle?by?cycle current limit in conjunction with
programming the current ratio as described above.
V in
Q3
V in
Q1
L1
V out
L2
Q2
R3
Q4
R1
C3
C2
R2
R
R
C
C1
C
R
C
Master
Error Amp
U2
?
+
V FB1
R4
R
V FB2
V REF2
?
+
Slave
Error Amp
U2
Internal
Reference
0.8 V
Figure 6. Two Phase Current Sharing Circuit
14.00
Channel 1 output current
12.00
10.00
8.00
Iout(1)
share begins to increase
Channel 2 output current
begins to level off at 5
6.00
4.00
2.00
0.00
0
Iout(2)
Iin(1)
Iin(2)
5 10 15
20
Amps
TOTAL OUTPUT CURRENT, AMPS
Figure 7. 70%/30% Current Sharing with Channel 2 Current Limiting
NOTE: Channel 1 input voltage = Channel 2 input voltage = 5.0 V
Output voltage = 1.5 V
http://onsemi.com
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