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参数资料
| 型号： | NCV4269DWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 20-SOIC |
| 产品变化通告： | NCV42xx Obsolescence 27/Apr/2011 |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 最高 45 V |
| 电压 - 压降（标准）： | 0.25V @ 100mA |
| 稳压器数量： | 1 |
| 电流 - 限制（最小）： | 150mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCV4269DWR2GOSCT |
NCV4269
APPLICATION DESCRIPTION
OUTPUT REGULATOR
The output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage V Q
increases above the reset threshold voltage V RT , the delay
timer D is started. When the voltage on the delay timer V D
passes V UD , the reset signal RO goes high. A discharge of
the delay timer V D is started when V Q drops and stays below
the reset threshold voltage V RT . When the voltage of the
delay timer V D drops below the lower threshold voltage V LD
the reset output voltage V RO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor
with an internal 20 k W pullup resistor connected to the
output Q, controlled by a low voltage detection circuit. The
circuit is functionally independent of the rest of the IC,
thereby guaranteeing that RO is valid for V Q as low as 1.0 V.
RESET ADJUST (R ADJ )
The reset threshold V RT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin R ADJ ,
as shown in Figure 21. The resistor divider keeps the voltage
above the V RADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
If the reset adjust option is not needed, the R ADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor C D ) on the reset output lead RO. The delay lead D
provides charge current I D,C (typically 6.5 m A) to the
external delay capacitor C D during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (V RT , reset
threshold voltage) has been violated. When the
delay capacitor discharges to V LD , the reset signal
RO pulls low.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor C D and the
charge current I D . The time is measured by the delay
capacitor voltage charging from the low level of V DSAT to
the higher level V UD . The time delay follows the equation:
td + [CD (VUD * VD, SAT)] ID, C (eq. 2)
Example:
Using C D = 100 nF.
Use the typical value for V D,SAT = 0.1 V.
Use the typical value for V UD = 1.8 V.
Use the typical value for Delay Charge Current I D = 6.5 m A.
td + [100 nF (1.8 * 0.1 V)] 6.5 m A + 26.2 ms (eq. 3)
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) RADJ2
(eq. 1)
V BAT
I
Q
V DD
C I *
0.1 m F
NCV4269
R ADJ
R ADJ1
R ADJ2
R SI1
C Q **
10 m F
C D
D
SI
R SI2
SO
GND
RO
I/O
I/O
*C I required if regulator is located far from the power supply filter.
** C Q required for Stability. Cap must operate at minimum temperature expected.
Figure 21. Application Diagram
http://onsemi.com
11
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