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参数资料
| 型号： | NCV565D2TR4G |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/15页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 1.5A D2PAK-5 |
| 标准包装： | 800 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.9 V ~ 7.7 V |
| 输入电压： | 2.5 V ~ 9 V |
| 电压 - 压降（标准）： | 0.9V @ 1.5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1.5A |
| 电流 - 限制（最小）： | 1.6A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-263-6，D²Pak（5 引线+接片），TO-263BA |
| 供应商设备封装： | D2PAK-5 |
| 包装： | 带卷 (TR) |
NCP565, NCV565
GEN
V out
? V CC
NCP565
V
Pulse
+
V in
Evaluation Board
GND
RL
+
GND
Scope Voltage Probe
Figure 19. Schematic for Transient Response Measurement
PCB Layout Considerations
Good PCB layout plays an important role in achieving
good load transient performance. Because it is very sensitive
to its PCB layout, particular care has to be taken when
tackling Printed Circuit Board (PCB) layout. The figures
below give an example of a layout where parasitic elements
are minimized. For microprocessor applications it is
customary to use an output capacitor network consisting of
several capacitors in parallel. This reduces the overall ESR
and reduces the instantaneous output voltage drop under
transient load conditions. The output capacitor network
should be as close as possible to the load for the best results.
The schematic of NCP565 typical application circuit, which
this PCB layout is base on, is shown in Figure 20. The output
voltage is set to 3.3 V for this demonstration board according
to the feedback resistors in the Table 1.
V in
2
V in
V out
4
V out
C 1
150 m
C 2
150 m
1
NCP565
NC Adj
GND
5
C 4
10 m
C 3
150 m
C 3
150 m
GND
3
R 2
15.8 k
R 1
42.2 k
GND
C 6
5.6 p
Figure 20. Schematic of NCP565 Typical Application Circuit
http://onsemi.com
8
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