参数资料
| 型号： | NCV7382DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER LIN ENH 8-SOIC |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 2,500 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | LIN |
| 电源电压： | 7 V ~ 18 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
NCV7382
http://onsemi.com
12
NOTE: The setting of the network time constant is
necessary in large networks (primarily resistance) and also
in small networks (primarily capacitance).
The NCV7382 meets the requirements for implementation
in RC-based slave nodes. The LIN Protocol Specification
requires the deviation of the slave node clock to the master
node clock after synchronization must not differ by more
than
"2%.
MIN/MAX SLOPE TIME CALCULATION
(In accordance to the LIN System Parameter Table)
Figure 8. Slope Time and Slew Rate Calculation
(In accordance to LIN physical layer specification 1.3)
60%
100%
0%
tsrec
tsdom
VBUS
40%
Vdom
60%
40%
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dV dt
+ 0.2 * Vswing (t40%-t60%)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
tslope + 5 * (t40%-t60%)
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
tslope + Vswing dV dt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because it's
a passive edge. In case of low battery voltages and high bus
loads the rising edge is only determined by the network. If the
rising edge slew rate exceeds the value of the dominant one,
the slew rate control determines the rising edge.
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