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参数资料
| 型号： | NCV7513FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/23页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER HEX LOSIDE 32-LQFP |
| 标准包装： | 2,000 |
| 系列： | FLEXMOS™ |
| 配置： | 低端 |
| 输入类型： | 非反相 |
| 延迟时间： | 1.0µs |
| 电流 - 峰： | 5.25mA |
| 配置数： | 6 |
| 输出数： | 6 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
NCV7513
Serial Data and Register Structure
The 16 ? bit data sent by the NCV7513 is always the
MSB
LSB
encoded 12 ? bit fault information, with the upper 4 bits
forced to zero. The 16 ? bit data received is decoded into a
B15 B14 B13 B12 B11 B10
0 0 0 0 CH5
B9 B8
CH4
B7 B6
CH3
B5 B4
CH2
B3 B2
CH1
B1 B0
CH0
4 ? bit address and a 6 ? bit data word (see Figure 11). The
upper four bits, beginning with the received MSB, are fully
decoded to address one of four programmable registers and
the lower six bits are decoded into data for the addressed
REGISTER SELECT
MSB
CHANNEL FAULT OUTPUT DATA
COMMAND INPUT DATA
LSB
register. Bit B15 must always be set to zero. The valid
register addresses are shown in Table 1. Each register is
B15 B14 B13 B12 B11 B10
0 A2 A1 A0 X X
B9
X
B8
X
B7
X
B6
X
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
next described in detail.
Table 1. Register Address Definitions
4 ? BIT ADDRESS
Figure 11. SPI Data Format
6 ? BIT INPUT DATA
B 15
A 2
A 1
A 0
D 5
D 4
D 3
D 2
D 1
D 0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Gate Select
Disable Mode
Refresh & Reference
Flag Mask
Null
16 ? BIT OUTPUT DATA
B 15
B 14
B 13
B 12
B 11
B 0
0
0
0
0
D 11
12 ? bit Fault Data
D 0
Gate Select – Register 0
Each GAT X output is turned on/off by programming its
respective G X bit (see Table 2). Setting a bit to 1 causes the
selected GAT X output to drive its external MOSFET’s gate
to V CC2 (ON). Setting a bit to 0 causes the selected GAT X
output to drive its external MOSFET’s gate to V SS (OFF).
Note that the actual state of the output depends on POR,
ENA X and shorted load fault states as later defined by
Equation 1. At powerup, each bit is set to 0 (all outputs
OFF).
to 1 causes the selected GAT X output to latch ? off when a
fault is detected. Setting a bit to 0 causes the selected GAT X
output to auto ? retry when a fault is detected. At powerup,
each bit is set to 0 (all outputs in auto ? retry mode).
Table 3. Disable Mode Register
A 2 A 1 A 0 D 5 D 4 D 3 D 2 D 1 D 0
0 0 1 M 5 M 4 M 3 M 2 M 1 M 0
0 = AUTO ? RETRY
1 = LATCH OFF
Table 2. Gate Select Register
A 2 A 1 A 0 D 5 D 4
D 3
D 2
D 1
D 0
Refresh and Reference – Register 2
Refresh time (auto ? retry mode) and shorted load fault
0 0 0 G 5 G 4 G 3 G 2 G 1 G 0
0 = GAT X OFF
1 = GAT X ON
Disable Mode – Register 1
The disable mode for shorted load faults is controlled by
each channel’s respective M X bit (see Table 3). Setting a bit
detection references are programmable in two groups of
three channels. Refresh time and the fault reference for
channels 5 ? 3 is programmed by R X bits 5 ? 3. Refresh time
and the fault reference for channels 2 ? 0 is programmed by
R X bits 2 ? 0 (see Table 4). At powerup, each bit is set to 0
(V FLT = 25% V FLTREF , t FR = 10 ms).
http://onsemi.com
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