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| 型号： | NCV8668ABD150R2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/18页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V .15A 8-SOIC |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 最高 40 V |
| 电压 - 压降（标准）： | 0.3V @ 150mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 150mA |
| 电流 - 限制（最小）： | 205mA |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
NCV8668
ELECTRICAL CHARACTERISTICS
V in = 13.2 V, C in = 0.1 m F, C out = 2.2 m F, for typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to 150 ° C; unless otherwise noted.
(Notes 10 and 11)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Disable and Quiescent Current
Disable Current
Quiescent Current (I q = I in – I out )
V EN = 0 V,T J < 85 ° C
I out = 100 m A, T J = 25 ° C
I out = 100 m A, T J v 125 ° C
I DIS
I q
?
?
?
?
38
?
1
43
44
m A
m A
Current Limit Protection
Current Limit
Short Circuit Current Limit
V out = 0.96 x V out_nom
V out = 0 V
I LIM
I SC
205
205
?
?
525
525
mA
mA
Reverse Output Current Protection
Reverse Output Current Protection
V EN = 0 V, I out = ? 1 mA
V out_rev
?
2
5.5
V
PSRR
Power Supply Ripple Rejection (Note 13) f = 100 Hz, 0.5V pp
PSRR
?
60
?
dB
Enable Thresholds
Enable Input Threshold Voltage
Logic High
Logic Low
V th(EN)
3
?
?
?
?
0.8
V
Enable Input Current
Logic High
Logic Low
V EN = 5 V
V EN = 0 V, T J < 85 ° C
I EN_ON
I EN_OFF
?
?
3
0.5
5
1
m A
Window Watchdog
Watchdog Mode Bit 1 Threshold Voltage
Voltage Increasing, Logic High
3.3 V
5.0 V
Voltage Decreasing, Logic Low
Watchdog Mode Bit 2 Threshold Voltage
Voltage Increasing, Logic High
3.3 V
5.0 V
Voltage Decreasing, Logic Low
Watchdog Input WDI Threshold Voltage
Voltage Increasing, Logic High
3.3 V
5.0 V
Voltage Decreasing, Logic Low
V WM1,H
V WM1,L
V WM2,H
V WM2,L
V WDI,H
V WDI,L
?
?
0.8
?
?
0.8
?
?
0.8
?
?
?
?
?
?
?
?
?
2.65
4.0
?
2.65
4.0
?
2.65
4.0
?
V
V
V
Watchdog Input WDI Current
Logic High
Logic Low
V WDI,H = 5 V
V WDI,L = 0 V, T J < 85 ° C
I WDI,H
I WDI,L
?
?
3
0.5
4
1
m A
Watchdog Sampling Time
Ignore Window Time
Open Window Time
Closed Window Time
Fast:
Slow:
Fast:
Slow:
Fast:
Slow:
Fast:
Slow:
WM2 = L
WM1 = L AND WM2 = H
WM2 = L
WM1 = L AND WM2 = H
WM2 = L
WM1 = L AND WM2 = H
WM2 = L
WM1 = L AND WM2 = H
t sam
t IW
t OW
t CW
0.4
0.8
25.6
51.2
25.6
51.2
25.6
51.2
0.5
1.0
32.0
64.0
32.0
64.0
32.0
64.0
0.6
1.2
38.4
76.8
38.4
76.8
38.4
76.8
ms
ms
ms
ms
10. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T A [ T J . Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12. Measured when output voltage falls 100 mV below the regulated voltage at V in = 13.2 V. If V out < 5 V, then V DO = V in – V out . Maximum dro-
pout voltage value is limited by minimum input voltage V in = 4.5 V recommended for guaranteed operation at maximum output current.
13. Values based on design and/or characterization.
14. Recommended for typical trigger time. T WD = t CW + 1/2 * t OW
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