参数资料
型号: NCV8668ABD250R2G
厂商: ON Semiconductor
文件页数: 13/18页
文件大小: 0K
描述: IC REG LDO 5V .15A 14SOIC
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 5V
输入电压: 最高 40 V
电压 - 压降(标准): 0.3V @ 150mA
稳压器数量: 1
电流 - 输出: 150mA
电流 - 限制(最小): 205mA
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 标准包装
其它名称: NCV8668ABD250R2GOSDKR
NCV8668
DEFINITIONS
General
All measurements are performed using short pulse low duty
cycle techniques to maintain junction temperature as close
as possible to ambient temperature.
Output Voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Load Regulation
The change in output voltage for a change in output current
measured for specific input voltage over operating ambient
temperature range.
Dropout Voltage
The input to output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. It is measured when the output drops 100 mV
below its nominal value. The junction temperature, load
current, and minimum input supply requirements affect the
dropout level.
Quiescent Currents
Quiescent Current (I q ) is the difference between the input
current (measured through the LDO input pin) and the
output current.
Current Limit and Short Circuit Current Limit
Current Limit is value of output current by which output
voltage drops below 96% of its nominal value. Short Circuit
Current Limit is output current value measured with output
of the regulator shorted to ground.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Line Transient Response
Typical output voltage overshoot and undershoot response
when the input voltage is excited with a given slope.
Load Transient Response
Typical output voltage overshoot and undershoot response
when the output current is excited with a given slope
between low ? load and high ? load conditions.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175 ° C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Package Power Dissipation
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
APPLICATIONS INFORMATION
The NCV8668 regulator is self ? protected with internal
thermal shutdown and internal current limit. Typical
characteristics are shown in Figures 4 to 27.
Input Decoupling (C in )
A ceramic or tantalum 0.1 m F capacitor is recommended
and should be connected close to the NCV8668 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
If extremely fast input voltage transients are expected then
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ m s for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (C out )
The NCV8668 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR versus Output
Current is shown in Figure 13. The minimum output
decoupling value is 2.2 m F and can be augmented to fulfill
stringent load transient requirements. The regulator works
with ceramic chip capacitors as well as tantalum devices.
Larger values improve noise rejection and load regulation
transient response.
Enable Operation
The Enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet.
Reset Operation
A reset signal is provided on the Reset Output (RO) pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 24. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to V OUT = 1.0 V. The Reset Output (RO) circuitry includes
http://onsemi.com
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