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| 型号： | NCV890100PDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.2A 8-SOICEP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 2MHz |
| 电流 - 输出： | 1.2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | NCV890100PDR2GOSDKR |
NCV890100
GENERAL INFORMATION
INPUT VOLTAGE
An Undervoltage Lockout (UVLO) circuit monitors the
input, and inhibits switching and resets the Soft ? start circuit
if there is insufficient voltage for proper regulation. The
NCV890100 can regulate a 3.3 V output with input voltages
above 4.5 V and a 5.0 V output with an input above 6.5 V.
The NCV890100 withstands input voltages up to 40 V.
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by a
factor of 2 when the input voltage exceeds the V IN
Frequency Foldback threshold V FLDUP (see Figure 25).
Frequency reduction is automatically terminated when the
input voltage drops back below the V IN Frequency Foldback
threshold V FLDDN .
Fsw
(MHz)
2
1
inductor current at which the power switch shuts off. The
Current Mode control method employed by the NCV890100
allows the use of a simple, Type II compensation to optimize
the dynamic response according to system requirements.
SLOPE COMPENSATION
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub ? harmonic oscillations. For 3.3 V and 5 V output
voltages, the recommended inductor value is 4.7 m H.
SHORT CIRCUIT FREQUENCY FOLDBACK
During severe output overloads or short circuits, the
NCV890100 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed. If the current is still too high after the
switching frequency folds back to 500 kHz, the regulator
enters an auto ? recovery burst mode that further reduces the
dissipated power.
CURRENT LIMITING
Due to the ripple on the inductor current, the average
4
18 20
36
VIN (V)
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 26 shows ? for a
ENABLE
Figure 25. NCV890100 Switching Frequency
Reduction at High Input Voltage
4.7 m H inductor ? how the variation of inductor peak current
with input voltage affects the maximum DC current the
NCV890100 can deliver to a load.
1.4
The NCV890100 is designed to accept either a logic level
signal or battery voltage as an Enable signal. EN low induces
a ’sleep mode’ which shuts off the regulator and minimizes
its supply current to a couple of m A typically (I qSD ) by
disabling all functions. Upon enabling, voltage is
established at the DRV pin, followed by a soft ? start of the
switching regulator output.
SOFT ? START
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft ? start circuit
1.3
1.2
1.1
1.0
0.9
0.8
0.7
(5 V OUT )
(3.3 V OUT )
0
ramps the switching regulator error amplifier reference
voltage to the final value. During soft ? start, the average
switching frequency is lower than its normal mode value
0.6
5
10
15 20 25
INPUT VOLTAGE (V)
30
35
40
(typically 2 MHz) until the output voltage approaches
regulation.
Figure 26. NCV890100 Load Current Capability
with 4.7 m H Inductor
ERROR AMPLIFIER
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
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