参数资料
型号: NL17SHT08P5T5G
厂商: ON Semiconductor
文件页数: 1/5页
文件大小: 0K
描述: IC GATE AND SGL 2INPUT SOT953
标准包装: 8,000
逻辑类型: 与门
电路数: 1
输入数: 2
电源电压: 3 V ~ 5.5 V
电流 - 静态(最大值): 1µA
输出电流高,低: 8mA,8mA
逻辑电平 - 低: 0.53 V ~ 0.8 V
逻辑电平 - 高: 1.4 V ~ 2 V
额定电压和最大 CL 时的最大传播延迟: 7.9ns @ 4.5V ~ 5.5V,50pF
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
供应商设备封装: SOT-953
封装/外壳: SOT-953
包装: 带卷 (TR)
Semiconductor Components Industries, LLC, 2011
August, 2011 Rev. 0
1
Publication Order Number:
NL17SHT08/D
NL17SHT08
2-Input AND Gate /
CMOS Logic Level Shifter
The NL17SHT08 is an advanced high speed CMOS 2input AND
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logiclevel translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the highvoltage power supply.
The NL17SHT08 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SHT08 to be used to interface 5 V circuits to 3 V circuits. The
output structures also provide protection when VCC = 0 V. These input
and output structures help prevent device destruction caused by supply
voltage input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
These are PbFree Devices
VCC
IN B
IN A
OUT Y
GND
IN A
IN B
OUT Y
&
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
1
2
34
5
PIN ASSIGNMENT
1
2
3IN B
IN A
GND
4
5VCC
OUT Y
L
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
L
H
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
SOT953
CASE 527AE
P
= Specific Device Code
M
= Month Code
PM
1
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