参数资料
型号: NLAST4053DTR2G
厂商: ON Semiconductor
文件页数: 1/14页
文件大小: 0K
描述: IC MUX/DEMUX TRIPLE 2X1 16TSSOP
产品变化通告: Product Obsolescence 30/Sept/2009
标准包装: 1
功能: 多路复用器/多路分解器
电路: 3 x 2:1
导通状态电阻: 33 欧姆
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 3 V ~ 5 V,±3 V
电流 - 电源: 40µA
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 标准包装
其它名称: NLAST4053DTR2GOSDKR
Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 1
1
Publication Order Number:
NLAST4053/D
NLAST4053
Analog Multiplexer/
Demultiplexer
TTL Compatible, Triple 2:1 Analog
Switch-Multiplexer Improved Process,
Sub-Micron Silicon Gate CMOS
The NLAST4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub-micron Silicon Gate CMOS
technology for lower RDS(on) resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to
±3 V to pass a 6 VPP signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
VEE, pin 7 to ground. For dual supply operation, VEE is tied to a
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit pins are standard TTL
level compatible. For CMOS compatibility see NLAS4053. Pin for
pin compatible with all industry standard versions of `4053.'
Improved RDS(on) Specifications
Pin for Pin Replacement for MAX4053 and MAX4053A
- One Half the Resistance Operating at 5.0 Volts
Single or Dual Supply Operation
- Single 3-5 Volt Operation, or Dual
±3 Volt Operation
- With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
- No Translators Needed
- Address and Inhibit Pins are Over-Voltage Tolerant and May Be
- Driven Up +6V Regardless of VCC
Address and Inhibit Pins are Standard TTL Compatible
- Greatly Improved Noise Margin Over MAX4053 and MAX4053A
- True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V
Improved Linearity Over Standard HC4053 Devices
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
This is a Pb-Free Device
http://onsemi.com
MARKING
DIAGRAM
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
TSSOP-16
DT SUFFIX
CASE 948F
AST
4053
ALYW
1
16
Device
Package
Shipping
ORDERING INFORMATION
NLAST4053DTR2G
TSSOP-16
(Pb-Free)
2500 / Tape &
Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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