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参数资料
| 型号： | NM24C05UFLZM8 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | PROM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | PLASTIC, SOIC-8 |
| 文件页数： | 10/13页 |
| 文件大小： | 89K |
| 代理商： | NM24C05UFLZM8 |
10
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NM24C04U/NM24C05U Rev. C.1
N
Write Operations
BYTE WRITE
For a write operation a second address field is required which is
a word address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page of memory. Upon
receipt of the byte address the NM24C04U/05U responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
NM24C04U/05U begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
NM24C04U/05U inputs are disabled, and the device will not
respond to any requests from the master. Refer to Figure 6 or the
address, acknowledge and data transfer sequence.
PAGE WRITE
The NM24C04U/05U is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the first
data byte is transferred, the master can transmit up to fifteen more
bytes. After the receipt of each byte, the NM24C04U/05U will
respond with an acknowledge.
After the receipt of each byte, the internal address counter
increments to the next address and the next SDA data is accepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will "roll over"
and the previously written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 7 for the address, acknowl-
edge, and data transfer sequence.
S
T
O
P
Bus Activity:
Master
SDA Line
Bus Activity:
NM24C04U/05U
DATA n + 15
DATA n + 1
DATA n
WORD ADDRESS (n)
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
A
C
K
DATA
A
C
K
A
C
K
S
T
A
R
T
WORD
ADDRESS
SLAVE
ADDRESS
Bus Activity:
Master
SDA Line
Bus Activity:
NM24C04U/05U
DS800008-15
DS800008-16
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host
’
s
write operation the NM24C04U/05U initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the NM24C04U/05U is still busy with the write
operation no ACK will be returned. If the NM24C04U/05U has
completed the write operation an ACK will be returned and the
host can then proceed with the next read or write operation.
Write Protection (NM24C05U Only)
Programming of the upper half of the memory will not take place
if the WP pin of the NM24C05U is connected to V
CC
. The
NM24C05U will accept slave and byte addresses; but if the
memory accessed is write protected by the WP pin, the NM24C05U
will not generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be started when
the stop condition is asserted.
Byte Write (Figure 6)
Page Write (Figure 7)
相关PDF资料 |
PDF描述 |
|---|---|
| NM24C05UFLZMT8 | I2C Serial EEPROM |
| NM24C05UFLZN | I2C Serial EEPROM |
| NM24C05UFLZVM8 | I2C Serial EEPROM |
| NM24C05UFLZVMT8 | I2C Serial EEPROM |
| NM24C05UFLZVN | I2C Serial EEPROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NM24C05UFLZMT8 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C05UFLZN | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C05UFLZVM8 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C05UFLZVMT8 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C05UFLZVN | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
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