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参数资料
| 型号： | NM24C32LN |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | PROM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 4K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件页数： | 5/12页 |
| 文件大小： | 87K |
| 代理商： | NM24C32LN |
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www.fairchildsemi.com
NM24C32 Rev. C.2
N
S
BACKGROUND INFORMATION (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional commu-
nication between Transmitter/Receiver using the SCL (clock) and
SDA (Data I/O) lines. All communication must be started with a valid
START condition, concluded with a STOP condition and acknowl-
edged by the Receiver with an ACKNOWLEDGE condition.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
slave address, must follow the START condition. For EEPROMs,
the first 4-bits of the slave address is '1010'. This is then followed
by the device selection bits A2, A1 and A0.The final bit in the slave
address determines the type of operation performed (READ/
WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The
slave address is then followed by two bytes that define the word
address, which is then followed by the data byte.
The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
4M bits in the Extended IIC protocol. EEPROM memory address-
ing is controlled by hardware configuring the A2, A1, and A0 pins
(Device Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (tied to V
SS
).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-
DRESS]-[BYTE ADDRESS]
Definitions
Word
8 bits (byte) of data
Page
32 sequential addresses (one byte
each) that may be programmed during
a "Page Write" programming cycle.
Master
Any IIC device CONTROLLING the
transfer of data (such as a microcon-
troller).
Slave
Device being controlled (EEPROMS
are always considered Slaves).
Transmitter
Device currently SENDING data on the
bus (may be either a Master or Slave).
Receiver
Device currently receiving data on the
bus (Master or Slave).
Pin Description
SERIAL CLOCK (SCL)
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a biderectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
SCL
SDA
IN
SDA
OUT
tF
tLOW
tHIGH
tR
tLOW
tAA
tDH
tBUF
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
Bus Timing
DS500073-3
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相关代理商/技术参数 |
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| NM24C65UEM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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