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参数资料
| 型号： | NM24C32UFN |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | PROM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 4K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 6/12页 |
| 文件大小： | 89K |
| 代理商： | NM24C32UFN |
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www.fairchildsemi.com
NM24C32U Rev. C.1
N
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to V
CC
or V
SS
to configure the EEPROM address for multiple device configura-
tion. A total of eight different devices can be attached to the same
SDA bus.
Write Protection (WP
)
If WP is tied to V
CC
, program WRITE operations onto the upper half
of the memory will not be executed. READ operations are always
available.
If WP is tied to V
SS
, normal memory operation is enabled, READ/
WRITE over the entire memory array.
This feature allows the user to assign the upper half of the memory
as ROM which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Device Operation
The NM24C32Uxxx supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data onto the bus
as a transmitter and the receiving devices as the receiver. The
device controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24C32Uxxx is considered a slave in
all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and reserved for indicating
start and stop conditions. Refer to Figures 2 and 3.
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
NM24C32Uxxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C32Uxxx to place the device
in the standby power mode.
Write Cycle Timing
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits. During the ninth clock
cycle the receiver will pull the SDA line LOW to acknowledge that
it received the eight bits of data. Refer to Figure 4
The NM24C32Uxxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
both the device and a WRITE operation have been selected, the
NM24C32Uxxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
In the READ mode the NM24C32Uxxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
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相关代理商/技术参数 |
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|---|---|
| NM24C65UEM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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| NM24C65ULN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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