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参数资料
| 型号： | NM24C65FLZEN |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | PROM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件页数： | 8/11页 |
| 文件大小： | 86K |
| 代理商： | NM24C65FLZEN |
8
www.fairchildsemi.com
NM24C65 Rev. C.3
N
S
Write Protection
Programming of the upper half of memory will not take place if the
WP pin is connected to V
CC
. The device will accept slave and word
addresses; but if the memory accessed is write protected by the
WP pin, the NM24C65xxx will not generate an acknowledge after
the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.
Low V
CC
Lockout
NM24C65xxx provides data security against inadvertent writes
that could potentially happen during the time the device is being
powered on, powered down and brown out conditions by monitor-
ing the V
voltage during a write cycle. Whenever a write cycle
is started, the built-in circuitry starts to monitor the V
CC
level
throughout the duration of the write command sequence until the
master issues the required STOP condition to start the actual
internal write operation. If the sensed V
CC
voltage is below 3.8V at
any point during this monitoring period, the device prohibits the
write operation and does not generate the ACK pulse. This low
V
CC
lockout feature is only available for standard 5V device.
Read Operation
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.
CURRENT ADDRESS READ
Internally the NM24C65xxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
one, the NM24C65xxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge acknowledge the
transfer but does generate a stop condition, and therefore discon-
tinues transmission. Refer to Figure 7for the sequence of ad-
dress, acknowledge and data transfer.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, slave address
and then the word address it is to read. After the word address
acknowledge, the master immediately reissues the start condition
and the slave address with the R/W bit set to "1". This will be
followed by an acknowledge from the NM24C65xxx and then by
the eight bit word. The master will not acknowledge the transfer
but does generate the stop condition, and therefore the
NM24C65xxx discontinues transmission. Refer to Figure 8 or the
address, acknowledge and data transfer sequence.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C65xxx continues to output data for each ac-
knowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
NM24C65xxx continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge and data
transfer sequence.
S
T
O
P
A
C
K
A
C
K
Bus Activity:
Master
SDA Line
1 0 1 0
0 0 0
Bus Activity
A
C
K
DATA n
DATA n+31
A
C
K
WORD
ADDRESS (1)
WORD
ADDRESS (0)
SLAVE
ADDRESS
S
T
A
R
T
DS500042-9
Page Write (Figure 6)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NM24C65UEM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| NM24C65UFM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| NM24C65ULEM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| NM24C65ULEN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| NM24C65ULN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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