- 您现在的位置：买卖IC网 > PDF目录363347 > NM24C65UFLN (FAIRCHILD SEMICONDUCTOR CORP) I2C Serial EEPROM PDF资料下载
参数资料
| 型号： | NM24C65UFLN |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | PROM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 8/11页 |
| 文件大小： | 89K |
| 代理商： | NM24C65UFLN |
8
www.fairchildsemi.com
NM24C65U Rev. B.1
N
Write Protection
Programming of the upper half of memory will not take place if the
WP pin is connected to V
CC
. The device will accept slave and word
addresses; but if the memory accessed is write protected by the
WP pin, the NM24C65Uxxx will not generate an acknowledge
after the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.
Low V
CC
Lockout
NM24C65UxHx (H option) protects against data corruption during
programming by preventing any programming operations if V
CC
drops below approximately 3.8V (V
Lockout trip level). This is
accomplished by monitoring the "READ/WRITE" (R/W) bit in the
SLAVE address and if the R/W bit is "0," indicating a programming
operation, the V
Lockout is activated. At that point, if the V
drops below the trip level, programming is inhibited and the device
does not issue an ACK (the output stays high). To restate, the V
CC
Lockout feature is active from the time a WRITE bit is received up
to the time that the Master's STOP condition is received (the STOP
condition turns on the V
PP
internal high voltage).
Once program-
ming has begun, the programming cycle cannot be inter-
rupted except by removal of V
CC
, which could result in data
corruption.
Read Operation
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.
CURRENT ADDRESS READ
Internally the NM24C65Uxxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
one, the NM24C65Uxxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge acknowledge the
transfer but does generate a stop condition, and therefore discon-
tinues transmission. Refer Figure 7for the Current Address Read
sequence.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, slave address
with the R/W bit set to "0" and then the word address it is to read
from. After the word address acknowledge, the master immedi-
ately reissues the start condition and the slave address with the
R/W bit set to "1". This will be followed by an acknowledge from the
NM24C65Uxxx and then by the eight bit data. The master will not
acknowledge the transfer but does generate the stop condition,
and therefore the NM24C65Uxxx discontinues transmission. Refer
Figure 8 or the Random Read sequence.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C65Uxxx continues to output data for each
acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
NM24C65Uxxx continues to output data for each acknowledge
received. Refer Figure 9for the Sequential Read sequence.
S
T
O
P
A
C
K
A
C
K
Bus Activity:
Master
SDA Line
1 0 1 0
0 0 0
Bus Activity
A
C
K
DATA n
DATA n+31
A
C
K
WORD
ADDRESS (1)
WORD
ADDRESS (0)
SLAVE
ADDRESS
S
T
A
R
T
DS800012-9
Page Write (Figure 6)
相关PDF资料 |
PDF描述 |
|---|---|
| NM24C65UFLVM8 | I2C Serial EEPROM |
| NM24C65UFLVN | I2C Serial EEPROM |
| NM24C65UFLZEM8 | I2C Serial EEPROM |
| NM24C65UFLZEN | I2C Serial EEPROM |
| NM24C65UFLZM8 | I2C Serial EEPROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NM24C65UFM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| NM24C65ULEM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| NM24C65ULEN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| NM24C65ULN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| NM24C65UM8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。