参数资料
型号: NP80N04NLG-S18-AY
厂商: Renesas Electronics America
文件页数: 5/12页
文件大小: 0K
描述: MOSFET N-CH 40V 80A TO-262
标准包装: 50
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 40V
电流 - 连续漏极(Id) @ 25° C: 80A
开态Rds(最大)@ Id, Vgs @ 25° C: 4.8 毫欧 @ 40A,10V
Id 时的 Vgs(th)(最大): 2.5V @ 250µA
闸电荷(Qg) @ Vgs: 135nC @ 10V
输入电容 (Ciss) @ Vds: 6900pF @ 25V
功率 - 最大: 1.8W
安装类型: 通孔
封装/外壳: TO-262-3,长引线,I²Pak,TO-262AA
供应商设备封装: TO-262
包装: 管件
NP80N04MLG, NP80N04NLG, NP80N04PLG
ELECTRICAL CHARACTERISTICS (T A = 25 ° C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
SYMBOL
I DSS
I GSS
V GS(th)
TEST CONDITIONS
V DS = 40 V, V GS = 0 V
V GS = ± 20 V, V DS = 0 V
V DS = V GS , I D = 250 μ A
MIN.
1.4
TYP.
MAX.
1
± 10
2.5
UNIT
μ A
μ A
V
Forward Transfer Admittance
Note
| y fs |
V DS = 5 V, I D = 35 A
25
64
S
Drain to Source On-state Resistance
Note
R DS(on)1
V GS = 10 V, I D = 40 A
3.8
4.8
m Ω
NP80N04MLG, NP80N04NLG
V GS = 10 V, I D = 40 A
3.3
4.5
m Ω
NP80N04PLG
R DS(on)2
V GS = 4.5 V, I D = 35 A
4.9
9.0
m Ω
NP80N04MLG, NP80N04NLG
V GS = 4.5 V, I D = 35 A
4.6
8.7
m Ω
NP80N04PLG
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
C iss
C oss
C rss
t d(on)
t r
t d(off)
t f
Q G
Q GS
Q GD
V DS = 25 V,
V GS = 0 V,
f = 1 MHz
V DD = 20 V, I D = 40 A,
V GS = 10 V,
R G = 0 Ω
V DD = 32 V,
V GS = 10 V,
I D = 80 A
4600
480
310
17
18
74
8
90
13
26
6900
720
560
37
45
148
20
135
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Note
V F(S-D)
t rr
Q rr
I F = 80 A, V GS = 0 V
I F = 80 A, V GS = 0 V,
di/dt = 100 A/ μ s
0.95
39
39
1.5
V
ns
nC
Note Pulsed test
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
PG.
D.U.T.
R G = 25 Ω
50 Ω
L
V DD
PG.
D.U.T.
R G
R L
V DD
V GS
Wave Form
V GS
0
10%
V GS
90%
V GS = 20 → 0 V
V DS
90%
90%
V DD
I D
I AS
BV DSS
V DS
V GS
0
τ
V DS
Wave Form
V DS
0
t d(on)
10%
t r
10%
t d(off)
t f
Starting T ch
τ = 1 μ s
Duty Cycle ≤ 1%
t on
t off
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I G = 2 mA
R L
PG.
50 Ω
V DD
Data Sheet D19797EJ1V0DS
3
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